X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fserial%2Farm_dcc.c;h=07981e18ee4991cfdbdcb93036ef996909b7791d;hb=368e86d9836aa044f2afb233e0445c8e4040b179;hp=29d929571df653199d61182b7f93ab9fb42b4524;hpb=e20cc2ca15b5b0644f51b6e58d530d70acd2bc00;p=u-boot diff --git a/drivers/serial/arm_dcc.c b/drivers/serial/arm_dcc.c index 29d929571d..07981e18ee 100644 --- a/drivers/serial/arm_dcc.c +++ b/drivers/serial/arm_dcc.c @@ -1,19 +1,9 @@ /* * Copyright (C) 2004-2007 ARM Limited. * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD + * Copyright (C) 2015 - 2016 Xilinx, Inc, Michal Simek * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 * * As a special exception, if other files instantiate templates or use macros * or inline functions from this file, or you compile this file and link it @@ -27,11 +17,12 @@ */ #include +#include #include -#if defined(CONFIG_CPU_V6) +#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7) /* - * ARMV6 + * ARMV6 & ARMV7 */ #define DCC_RBIT (1 << 30) #define DCC_WBIT (1 << 29) @@ -61,6 +52,22 @@ #define status_dcc(x) \ __asm__ volatile ("mrc p14, 0, %0, c14, c0, 0\n" : "=r" (x)) +#elif defined(CONFIG_CPU_ARMV8) +/* + * ARMV8 + */ +#define DCC_RBIT (1 << 30) +#define DCC_WBIT (1 << 29) + +#define write_dcc(x) \ + __asm__ volatile ("msr dbgdtrtx_el0, %0\n" : : "r" (x)) + +#define read_dcc(x) \ + __asm__ volatile ("mrs %0, dbgdtrrx_el0\n" : "=r" (x)) + +#define status_dcc(x) \ + __asm__ volatile ("mrs %0, mdccsr_el0\n" : "=r" (x)) + #else #define DCC_RBIT (1 << 0) #define DCC_WBIT (1 << 1) @@ -89,12 +96,7 @@ #define TIMEOUT_COUNT 0x4000000 -static int arm_dcc_init(void) -{ - return 0; -} - -static int arm_dcc_getc(void) +static int arm_dcc_getc(struct udevice *dev) { int ch; register unsigned int reg; @@ -107,7 +109,7 @@ static int arm_dcc_getc(void) return ch; } -static void arm_dcc_putc(char ch) +static int arm_dcc_putc(struct udevice *dev, char ch) { register unsigned int reg; unsigned int timeout_count = TIMEOUT_COUNT; @@ -118,47 +120,57 @@ static void arm_dcc_putc(char ch) break; } if (timeout_count == 0) - return; + return -EAGAIN; else write_dcc(ch); -} -static void arm_dcc_puts(const char *s) -{ - while (*s) - arm_dcc_putc(*s++); + return 0; } -static int arm_dcc_tstc(void) +static int arm_dcc_pending(struct udevice *dev, bool input) { register unsigned int reg; - can_read_dcc(reg); + if (input) { + can_read_dcc(reg); + } else { + can_write_dcc(reg); + } return reg; } -static void arm_dcc_setbrg(void) -{ -} +static const struct dm_serial_ops arm_dcc_ops = { + .putc = arm_dcc_putc, + .pending = arm_dcc_pending, + .getc = arm_dcc_getc, +}; + +static const struct udevice_id arm_dcc_ids[] = { + { .compatible = "arm,dcc", }, + { } +}; -static struct serial_device arm_dcc_drv = { +U_BOOT_DRIVER(serial_dcc) = { .name = "arm_dcc", - .start = arm_dcc_init, - .stop = NULL, - .setbrg = arm_dcc_setbrg, - .putc = arm_dcc_putc, - .puts = arm_dcc_puts, - .getc = arm_dcc_getc, - .tstc = arm_dcc_tstc, + .id = UCLASS_SERIAL, + .of_match = arm_dcc_ids, + .ops = &arm_dcc_ops, + .flags = DM_FLAG_PRE_RELOC, }; -void arm_dcc_initialize(void) +#ifdef CONFIG_DEBUG_UART_ARM_DCC + +#include + +static inline void _debug_uart_init(void) { - serial_register(&arm_dcc_drv); } -__weak struct serial_device *default_serial_console(void) +static inline void _debug_uart_putc(int ch) { - return &arm_dcc_drv; + arm_dcc_putc(NULL, ch); } + +DEBUG_UART_FUNCS +#endif