X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fvideo%2Fomap3_dss.c;h=6efba122e7876fc24b3d8d7444be66bcc54995c8;hb=9909aebc9d0820aa4f35308f3d8a8d7821e9f8e5;hp=b322cc35796c24294105d66da559d2ab119d2cad;hpb=684cad5717ea5887a09f3c67732a17774a658b34;p=u-boot

diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c
index b322cc3579..6efba122e7 100644
--- a/drivers/video/omap3_dss.c
+++ b/drivers/video/omap3_dss.c
@@ -28,10 +28,9 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/dss.h>
+#include <video_fb.h>
 
-/*
- * Configure VENC for a given Mode (NTSC / PAL)
- */
+/* Configure VENC for a given Mode (NTSC / PAL) */
 void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
 				u32 height, u32 width)
 {
@@ -64,10 +63,8 @@ void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
 	writel(venc_cfg->savid__eavid, &venc->savid__eavid);
 	writel(venc_cfg->flen__fal, &venc->flen__fal);
 	writel(venc_cfg->lal__phase_reset, &venc->lal__phase_reset);
-	writel(venc_cfg->hs_int_start_stop_x,
-				&venc->hs_int_start_stop_x);
-	writel(venc_cfg->hs_ext_start_stop_x,
-				&venc->hs_ext_start_stop_x);
+	writel(venc_cfg->hs_int_start_stop_x, &venc->hs_int_start_stop_x);
+	writel(venc_cfg->hs_ext_start_stop_x, &venc->hs_ext_start_stop_x);
 	writel(venc_cfg->vs_int_start_x, &venc->vs_int_start_x);
 	writel(venc_cfg->vs_int_stop_x__vs_int_start_y,
 			&venc->vs_int_stop_x__vs_int_start_y);
@@ -93,39 +90,78 @@ void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
 	writel(venc_cfg->dac_b__dac_c, &venc->dac_b__dac_c);
 
 	/* Configure DSS for VENC Settings */
-	writel(VENC_DSS_CONFIG, &dss->control);
+	writel(VENC_CLK_ENABLE | DAC_DEMEN | DAC_POWERDN | VENC_OUT_SEL,
+			&dss->control);
 
 	/* Configure height and width for Digital out */
-	writel(((height << DIG_LPP_SHIFT) | width), &dispc->size_dig);
+	writel(height << DIG_LPP_SHIFT | width, &dispc->size_dig);
 }
 
-/*
- * Configure Panel Specific Parameters
- */
+/* Configure Panel Specific Parameters */
 void omap3_dss_panel_config(const struct panel_config *panel_cfg)
 {
 	struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
+	struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE;
+
+	writel(DSS_SOFTRESET, &dss->sysconfig);
+	while (!(readl(&dss->sysstatus) & DSS_RESETDONE))
+		;
 
 	writel(panel_cfg->timing_h, &dispc->timing_h);
 	writel(panel_cfg->timing_v, &dispc->timing_v);
 	writel(panel_cfg->pol_freq, &dispc->pol_freq);
 	writel(panel_cfg->divisor, &dispc->divisor);
 	writel(panel_cfg->lcd_size, &dispc->size_lcd);
-	writel((panel_cfg->load_mode << FRAME_MODE_SHIFT), &dispc->config);
-	writel(((panel_cfg->panel_type << TFTSTN_SHIFT) |
-		(panel_cfg->data_lines << DATALINES_SHIFT)), &dispc->control);
+	writel(panel_cfg->load_mode << LOADMODE_SHIFT, &dispc->config);
+	writel(panel_cfg->panel_type << TFTSTN_SHIFT |
+		panel_cfg->data_lines << DATALINES_SHIFT, &dispc->control);
 	writel(panel_cfg->panel_color, &dispc->default_color0);
+	writel((u32) panel_cfg->frame_buffer, &dispc->gfx_ba0);
+
+	if (!panel_cfg->frame_buffer)
+		return;
+
+	writel(panel_cfg->gfx_format | GFX_ENABLE, &dispc->gfx_attributes);
+	writel(1, &dispc->gfx_row_inc);
+	writel(1, &dispc->gfx_pixel_inc);
+	writel(panel_cfg->lcd_size, &dispc->gfx_size);
 }
 
-/*
- * Enable LCD and DIGITAL OUT in DSS
- */
+/* Enable LCD and DIGITAL OUT in DSS */
 void omap3_dss_enable(void)
 {
 	struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
-	u32 l = 0;
+	u32 l;
 
 	l = readl(&dispc->control);
-	l |= DISPC_ENABLE;
+	l |= LCD_ENABLE | GO_LCD | DIG_ENABLE | GO_DIG | GP_OUT0 | GP_OUT1;
 	writel(l, &dispc->control);
 }
+
+#ifdef CONFIG_CFB_CONSOLE
+int __board_video_init(void)
+{
+	return -1;
+}
+
+int board_video_init(void)
+			__attribute__((weak, alias("__board_video_init")));
+
+void *video_hw_init(void)
+{
+	static GraphicDevice dssfb;
+	GraphicDevice *pGD = &dssfb;
+	struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
+
+	if (board_video_init() || !readl(&dispc->gfx_ba0))
+		return NULL;
+
+	pGD->winSizeX = (readl(&dispc->size_lcd) & 0x7FF) + 1;
+	pGD->winSizeY = ((readl(&dispc->size_lcd) >> 16) & 0x7FF) + 1;
+	pGD->gdfBytesPP = 4;
+	pGD->gdfIndex = GDF_32BIT_X888RGB;
+	pGD->frameAdrs = readl(&dispc->gfx_ba0);
+
+	return pGD;
+}
+#endif