X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=include%2Fconfigs%2FCPCI405DT.h;h=e2652e6aa6e130473399f8b16ca6958cb2ac0059;hb=f2c2a937d8c4a44f63ff88bf82023e03a29497a2;hp=42ec0801ad79edffc51d5d4b37b7ce309645f130;hpb=6f35c53166213c24a5a0e2390ed861136ff73870;p=u-boot

diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
index 42ec0801ad..e2652e6aa6 100644
--- a/include/configs/CPCI405DT.h
+++ b/include/configs/CPCI405DT.h
@@ -63,25 +63,37 @@
 
 #define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
 
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
-				 CONFIG_BOOTP_DNS | \
-				 CONFIG_BOOTP_DNS2 | \
-				 CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_PCI	| \
-				CFG_CMD_IRQ	| \
-				CFG_CMD_IDE	| \
-				CFG_CMD_FAT	| \
-				CFG_CMD_ELF	| \
-				CFG_CMD_DATE	| \
-				CFG_CMD_JFFS2	| \
-				CFG_CMD_I2C	| \
-				CFG_CMD_MII	| \
-				CFG_CMD_PING	| \
-				CFG_CMD_BSP	| \
-				CFG_CMD_EEPROM	)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
 
 #if 0 /* test-only */
 #define CONFIG_NETCONSOLE
@@ -99,9 +111,6 @@
 
 #undef  CONFIG_AUTO_UPDATE              /* autoupdate via compactflash  */
 
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
 #define CFG_NAND_LEGACY
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
@@ -119,7 +128,7 @@
 #define CFG_PROMPT_HUSH_PS2	"> "
 #endif
 
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
 #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
@@ -175,7 +184,6 @@
 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 
 #define CONFIG_PCI			/* include pci support	        */
-#define CFG_PCI_PRE_INIT                /* pci interrupt mapping etc.   */
 #define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
 #define CONFIG_PCI_PNP			/* do pci plug-and-play         */
 					/* resource configuration       */
@@ -319,7 +327,7 @@
 #define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
 					/* have only 8kB, 16kB is save here	*/
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif