X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=include%2Fconfigs%2FSIMPC8313.h;h=70b7489ab1c90f95d1c60dd14de74224e490795c;hb=4ad0df2b7c79b5514795202d59a4287bc73cb41f;hp=84af8df9c999eec406187bfffb1c6e28e10fda33;hpb=3699c28e6d16b563629c285311a0ce62a2c4c5d0;p=u-boot

diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
index 84af8df9c9..70b7489ab1 100644
--- a/include/configs/SIMPC8313.h
+++ b/include/configs/SIMPC8313.h
@@ -37,6 +37,7 @@
 #define CONFIG_MPC8313			1
 
 #define CONFIG_PCI
+#define CONFIG_FSL_ELBC			1
 
 #define CONFIG_MISC_INIT_R
 
@@ -126,6 +127,7 @@
 #else
 #define CONFIG_SYS_NAND_BASE		0xE2800000
 #endif
+#define CONFIG_SYS_FPGA_BASE		0xFF000000
 
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define NAND_MAX_CHIPS			1
@@ -184,6 +186,16 @@
 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM	CONFIG_SYS_LBLAWBAR0_PRELIM
 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM	CONFIG_SYS_LBLAWAR0_PRELIM
 
+#define CONFIG_SYS_BR1_PRELIM		( CONFIG_SYS_FPGA_BASE \
+					| BR_PS_16 \
+					| BR_MS_UPMA \
+					| BR_V )
+#define CONFIG_SYS_OR1_PRELIM		( OR_AM_2MB \
+					| OR_UPM_BCTLD)
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_FPGA_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_2MB)
+
 /*
  * JFFS2 configuration
  */
@@ -407,7 +419,8 @@
 				| SICRH_ETSEC2_G	\
 				| SICRH_TSOBI1		\
 				| SICRH_TSOBI2 )
-#define CONFIG_SYS_SICRL	(SICRL_USBDR		\
+#define CONFIG_SYS_SICRL	( SICRL_LBC		\
+				| SICRL_USBDR_10	\
 				| SICRL_ETSEC2_A )
 
 #define CONFIG_SYS_HID0_INIT	0x000000000