X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=include%2Fconfigs%2FSandpoint8240.h;h=f54fcb33e57f0aacb490b966f14fc82ce6018163;hb=f7fa2f3740083bbdf9f57b0e0495eb07899db5e8;hp=e2d45b1c8266ca57b33097ceab15d532bbc04c79;hpb=553f09823cced77296825f615f00321d932bf914;p=u-boot diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h index e2d45b1c82..f54fcb33e5 100644 --- a/include/configs/Sandpoint8240.h +++ b/include/configs/Sandpoint8240.h @@ -40,6 +40,7 @@ #define CONFIG_SANDPOINT 1 #define CONFIG_SYS_TEXT_BASE 0xFFF00000 +#define CONFIG_SYS_LDSCRIPT "board/sandpoint/u-boot.lds" #if 0 #define USE_DINK32 1 @@ -128,7 +129,6 @@ #define CONFIG_PCI /* include pci support */ #undef CONFIG_PCI_PNP -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ #define CONFIG_EEPRO100 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ @@ -155,20 +155,17 @@ #define CONFIG_SYS_RAMBOOT 1 #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #else #undef CONFIG_SYS_RAMBOOT #define CONFIG_SYS_MONITOR_LEN 0x00030000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -/*#define CONFIG_SYS_GBL_DATA_SIZE 256*/ -#define CONFIG_SYS_GBL_DATA_SIZE 128 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #endif @@ -229,7 +226,6 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } /*----------------------------------------------------------------------- @@ -237,7 +233,7 @@ */ -#define CONFIG_WINBOND_83C553 1 /*has a winbond bridge */ +/* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */ #define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ #define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ #define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */