X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=include%2Fconfigs%2Fads5121.h;h=ce458ae5b8789200ebee271ea9c1ded8c7b0f2b0;hb=7232a2724ccc9dcbc3ec4ef84ada02f13ccd1238;hp=a1b8eefa02c228668868d1358b5f36d833c29529;hpb=8993e54b6f397973794f3d6f47d3b3c0c98dd4f6;p=u-boot diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index a1b8eefa02..ce458ae5b8 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -65,48 +65,49 @@ #define CFG_SDRAM_BASE CFG_DDR_BASE /* DDR Controller Configuration - -SYS_CFG: - [31:31] MDDRC Soft Reset: Diabled - [30:30] DRAM CKE pin: Enabled - [29:29] DRAM CLK: Enabled - [28:28] Command Mode: Enabled (For initialization only) - [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] - [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] - [20:19] Read Test: DON'T USE - [18:18] Self Refresh: Enabled - [17:17] 16bit Mode: Disabled - [16:13] Ready Delay: 2 - [12:12] Half DQS Delay: Disabled - [11:11] Quarter DQS Delay: Disabled - [10:08] Write Delay: 2 - [07:07] Early ODT: Disabled - [06:06] On DIE Termination: Disabled - [05:05] FIFO Overflow Clear: DON'T USE here - [04:04] FIFO Underflow Clear: DON'T USE here - [03:03] FIFO Overflow Pending: DON'T USE here - [02:02] FIFO Underlfow Pending: DON'T USE here - [01:01] FIFO Overlfow Enabled: Enabled - [00:00] FIFO Underflow Enabled: Enabled - TIME_CFG0 - [31:16] DRAM Refresh Time: 0 CSB clocks - [15:8] DRAM Command Time: 0 CSB clocks - [07:00] DRAM Precharge Time: 0 CSB clocks - TIME_CFG1 - [31:26] DRAM tRFC: - [25:21] DRAM tWR1: - [20:17] DRAM tWRT1: - [16:11] DRAM tDRR: - [10:05] DRAM tRC: - [04:00] DRAM tRAS: - TIME_CFG2 - [31:28] DRAM tRCD: - [27:23] DRAM tFAW: - [22:19] DRAM tRTW1: - [18:15] DRAM tCCD: - [14:10] DRAM tRTP: - [09:05] DRAM tRP: - [04:00] DRAM tRPA */ + * + * SYS_CFG: + * [31:31] MDDRC Soft Reset: Diabled + * [30:30] DRAM CKE pin: Enabled + * [29:29] DRAM CLK: Enabled + * [28:28] Command Mode: Enabled (For initialization only) + * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] + * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] + * [20:19] Read Test: DON'T USE + * [18:18] Self Refresh: Enabled + * [17:17] 16bit Mode: Disabled + * [16:13] Ready Delay: 2 + * [12:12] Half DQS Delay: Disabled + * [11:11] Quarter DQS Delay: Disabled + * [10:08] Write Delay: 2 + * [07:07] Early ODT: Disabled + * [06:06] On DIE Termination: Disabled + * [05:05] FIFO Overflow Clear: DON'T USE here + * [04:04] FIFO Underflow Clear: DON'T USE here + * [03:03] FIFO Overflow Pending: DON'T USE here + * [02:02] FIFO Underlfow Pending: DON'T USE here + * [01:01] FIFO Overlfow Enabled: Enabled + * [00:00] FIFO Underflow Enabled: Enabled + * TIME_CFG0 + * [31:16] DRAM Refresh Time: 0 CSB clocks + * [15:8] DRAM Command Time: 0 CSB clocks + * [07:00] DRAM Precharge Time: 0 CSB clocks + * TIME_CFG1 + * [31:26] DRAM tRFC: + * [25:21] DRAM tWR1: + * [20:17] DRAM tWRT1: + * [16:11] DRAM tDRR: + * [10:05] DRAM tRC: + * [04:00] DRAM tRAS: + * TIME_CFG2 + * [31:28] DRAM tRCD: + * [27:23] DRAM tFAW: + * [22:19] DRAM tRTW1: + * [18:15] DRAM tCCD: + * [14:10] DRAM tRTP: + * [09:05] DRAM tRP: + * [04:00] DRAM tRPA + */ #define CFG_MDDRC_SYS_CFG 0xF8604200 #define CFG_MDDRC_SYS_CFG_RUN 0xE8604200 @@ -230,9 +231,17 @@ SYS_CFG: #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #if 0 -#define CFG_I2C_NOPROBES {{0,0x69}} * Don't probe these addrs */ +#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ #endif +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */ +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */ + /* * Ethernet configuration */ @@ -240,7 +249,6 @@ SYS_CFG: #define CONFIG_NET_MULTI #define CONFIG_PHY_ADDR 0x1 #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_ETHADDR 00:e0:5e:00:e5:14 #if 0 /* @@ -266,29 +274,28 @@ SYS_CFG: #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_EEPROM + #if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_NET \ - | CFG_CMD_PING \ - ) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_NET \ - | CFG_CMD_PING \ - | CFG_CMD_MII \ - | CFG_CMD_I2C) +#define CONFIG_CMD_PCI #endif -#include - /* * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock. * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set * to 0xFFFF, watchdog timeouts after about 64s. For details refer * to chapter 36 of the MPC5121e Reference Manual. */ -#define CONFIG_WATCHDOG /* enable watchdog */ +/* #define CONFIG_WATCHDOG */ /* enable watchdog */ #define CFG_WATCHDOG_VALUE 0xFFFF /* @@ -298,10 +305,10 @@ SYS_CFG: #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#ifdef CONFIG_CMD_KGDB + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif @@ -320,7 +327,7 @@ SYS_CFG: /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif @@ -333,10 +340,10 @@ SYS_CFG: * * Boot Flags */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -344,21 +351,14 @@ SYS_CFG: /* * Environment Configuration */ -#define CONFIG_ENV_OVERWRITE +#define CONFIG_TIMESTAMP #define CONFIG_HOSTNAME ads5121 -#define CONFIG_ROOTPATH /nfsroot/rootfs -#define CONFIG_BOOTFILE uImage - -#define CONFIG_IPADDR 192.168.160.77 -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_BOOTFILE ads5121/uImage -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */ -//#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ -#define CONFIG_BOOTDELAY -1 +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 @@ -368,43 +368,55 @@ SYS_CFG: "echo" #define CONFIG_EXTRA_ENV_SETTINGS \ + "u-boot_addr_r=200000\0" \ + "kernel_addr_r=200000\0" \ + "fdt_addr_r=400000\0" \ + "ramdisk_addr_r=500000\0" \ + "u-boot_addr=FFF00000\0" \ + "kernel_addr=FC000000\0" \ + "fdt_addr=FC2C0000\0" \ + "ramdisk_addr=FC300000\0" \ + "ramdiskfile=ads5121/uRamdisk\0" \ + "fdtfile=ads5121/ads5121.dtb\0" \ + "u-boot=ads5121/u-boot.bin\0" \ "netdev=eth0\0" \ + "consdev=ttyPSC0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "addtty=setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ + "bootm ${kernel_addr_r} - ${fdt_addr}\0" \ "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "load=tftp 100000 /tftpboot/ads5121/u-boot.bin\0" \ - "update=protect off fff00000 fff3ffff; " \ - "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ - "upd=run load;run update\0" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ + "run nfsargs addip addtty;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "net_self=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ + "tftp ${fdt_addr} ${fdtfile};" \ + "run ramargs addip addtty;" \ + "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr}\0"\ + "load=tftp ${u-boot_addr} ${u-boot}\0" \ + "update=protect off ${u-boot_addr} +${filesize};" \ + "era ${u-boot_addr} +${filesize};" \ + "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ + "upd=run load update\0" \ "" -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - #define CONFIG_BOOTCOMMAND "run flash_self" +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#define OF_CPU "PowerPC,5121@0" +#define OF_SOC "soc5121@80000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc5121@80000000/serial@11300" + #endif /* __CONFIG_H */