X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=include%2Fconfigs%2Fcorenet_ds.h;h=115df2a0cd387fb70011cddba03a9a664d00f8c3;hb=d26e34c4c4b6473fdbd412a3b2dc33a94b08e8ff;hp=88750e057e8fd0a4834f2fe1de10d52d2fd8996e;hpb=1254ff97abb7606ccd0d7bdcd9f22581c50fe535;p=u-boot diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 88750e057e..115df2a0cd 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -10,25 +10,31 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_DISPLAY_BOARDINFO - #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_RAMBOOT_PBL +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#ifdef CONFIG_NAND +#define CONFIG_RAMBOOT_NAND +#endif +#define CONFIG_BOOTSCRIPT_COPY_RAM +#else #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg -#if defined(CONFIG_P3041DS) +#if defined(CONFIG_TARGET_P3041DS) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg -#elif defined(CONFIG_P4080DS) +#elif defined(CONFIG_TARGET_P4080DS) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg -#elif defined(CONFIG_P5020DS) +#elif defined(CONFIG_TARGET_P5020DS) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg -#elif defined(CONFIG_P5040DS) +#elif defined(CONFIG_TARGET_P5040DS) #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg #endif #endif +#endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ @@ -40,9 +46,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */ @@ -58,14 +61,11 @@ #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ -#define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_FSL_LAW /* Use common FSL init code */ - #define CONFIG_ENV_OVERWRITE #ifdef CONFIG_SYS_NO_FLASH @@ -176,7 +176,6 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 @@ -321,7 +320,6 @@ * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -334,18 +332,6 @@ #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_OF_STDOUT_VIA_ALIAS - -/* new uImage format support */ -#define CONFIG_FIT -#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ - /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_FSL @@ -407,9 +393,6 @@ /* * eSPI - Enhanced SPI */ -#define CONFIG_FSL_ESPI -#define CONFIG_SPI_FLASH_SPANSION -#define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 @@ -565,8 +548,6 @@ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_E1000 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION @@ -588,7 +569,6 @@ #define CONFIG_LBA48 #define CONFIG_CMD_SATA #define CONFIG_DOS_PARTITION -#define CONFIG_CMD_EXT2 #endif #ifdef CONFIG_FMAN_ENET @@ -619,14 +599,8 @@ /* * Command line configuration. */ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_ERRATA -#define CONFIG_CMD_GREPENV #define CONFIG_CMD_IRQ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO #ifdef CONFIG_PCI @@ -640,22 +614,16 @@ #define CONFIG_HAS_FSL_MPH_USB #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -#define CONFIG_CMD_USB -#define CONFIG_USB_STORAGE #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_CMD_EXT2 #endif #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION #endif @@ -703,11 +671,10 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 -#ifdef CONFIG_P4080DS +#ifdef CONFIG_TARGET_P4080DS #define __USB_PHY_TYPE ulpi #else #define __USB_PHY_TYPE utmi @@ -730,7 +697,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=p4080ds/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=p4080ds/p4080ds.dtb\0" \ "bdev=sda3\0" @@ -762,8 +729,4 @@ #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */