X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=include%2Fconfigs%2Fethernut5.h;h=b79000e706a5cac3a672642ffdb505a6ef88dcbe;hb=0d1ea05210f3221667f8085cf167f23f336ca0c0;hp=7fd0b51860fd690a662121ef3656eacea5b677bd;hpb=c0e5dd88c438a41bf180dde0c2dc4c67dcd8058d;p=u-boot

diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index 7fd0b51860..b79000e706 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -12,6 +12,8 @@
 
 #include <asm/hardware.h>
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 /* The first stage boot loader expects u-boot running at this address. */
 #define CONFIG_SYS_TEXT_BASE	0x27000000	/* 16MB available */
 
@@ -23,15 +25,12 @@
 #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
 
 /* CPU information */
-#define CONFIG_ARM926EJS
-#define CONFIG_AT91FAMILY
 #define CONFIG_DISPLAY_CPUINFO		/* Display at console. */
 #define CONFIG_ARCH_CPU_INIT
 
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768	/* slow clock xtal */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	18432000 /* 18.432 MHz crystal */
-#define CONFIG_SYS_HZ			1000
 
 /* 32kB internal SRAM */
 #define CONFIG_SRAM_BASE	0x00300000 /*AT91SAM9XE_SRAM_BASE */
@@ -79,7 +78,6 @@
 
 /* SPI */
 #define CONFIG_ATMEL_SPI
-#define CONFIG_SYS_SPI_WRITE_TOUT	(5 * CONFIG_SYS_HZ)
 #define AT91_SPI_CLK			15000000
 
 /* Serial port */
@@ -150,12 +148,11 @@
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTC, 14
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PC(14)
 #endif
 
 /* JFFS2 */
 #ifdef CONFIG_CMD_JFFS2
-#define CONFIG_MTD_NAND_ECC_JFFS2
 #define CONFIG_JFFS2_CMDLINE
 #define CONFIG_JFFS2_NAND
 #endif