X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=include%2Fconfigs%2Fo2dnt.h;h=5c05a745dbb82b4555cd46783a1db95b6e44b76e;hb=007d67da94db86989c3d0ad0a9728391b7eed02b;hp=04d7d8a28280b4b5dfd1ed03fffc517dc578ae0d;hpb=d9f2f5008c32c8373d68a4c8e14f50a469965a23;p=u-boot

diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h
index 04d7d8a282..5c05a745db 100644
--- a/include/configs/o2dnt.h
+++ b/include/configs/o2dnt.h
@@ -117,16 +117,16 @@
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=$(serverip):$(rootpath)\0"			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs $(bootargs) "				\
-		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
-		":$(hostname):$(netdev):off panic=1\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
 	"flash_nfs=run nfsargs addip;"					\
-		"bootm $(kernel_addr)\0"				\
+		"bootm ${kernel_addr}\0"				\
 	"flash_self=run ramargs addip;"					\
-		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
-	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
 	"rootpath=/opt/eldk/ppc_82xx\0"					\
 	"bootfile=/tftpboot/MPC5200/uImage\0"				\
 	""
@@ -137,8 +137,20 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+
+#if defined(CFG_IPBSPEED_133)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
+ * been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CFG_PCISPEED_66			/* define for 66MHz speed */
+#endif
 #endif
+
 /*
  * I2C configuration
  */
@@ -226,7 +238,7 @@
  * GPIO configuration
  */
 /*#define CFG_GPS_PORT_CONFIG	0x10002004 */
-#define CFG_GPS_PORT_CONFIG	0x00002004	/* no CAN */
+#define CFG_GPS_PORT_CONFIG	0x00002006	/* no CAN */
 
 /*
  * Miscellaneous configurable options
@@ -263,7 +275,16 @@
 
 #define CFG_BOOTCS_START	CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG		0x00047801
+
+#ifdef CFG_PCISPEED_66
+/*
+ * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
+ */
+#define CFG_BOOTCS_CFG		0x00057801 /* for pci_clk = 66 MHz */
+#else
+#define CFG_BOOTCS_CFG		0x00047801 /* for pci_clk = 33 MHz */
+#endif
+
 #define CFG_CS0_START		CFG_FLASH_BASE
 #define CFG_CS0_SIZE		CFG_FLASH_SIZE