X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=include%2Fconfigs%2Fsbc8548.h;h=2209ddf8238db9010cc54111d2e9da177e8c6246;hb=039cbaefcf57338cc9b6a3c656db64e7907838db;hp=1df2225a77887e2c50508b2e84b4b637ffaca4cc;hpb=5f4c6f0db930646e9ca3b479b5fe9b8d2691fa77;p=u-boot

diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 1df2225a77..2209ddf823 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -119,9 +119,17 @@
 /* DDR Setup */
 #define CONFIG_FSL_DDR2
 #undef CONFIG_FSL_DDR_INTERACTIVE
+#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
+/*
+ * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
+ * to collide, meaning you couldn't reliably read either. So
+ * physically remove the LBC PC100 SDRAM module from the board
+ * before enabling the two SPD options below, or check that you
+ * have the hardware fix on your board via "i2c probe" and looking
+ * for a device at 0x53.
+ */
 #undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
 #undef CONFIG_DDR_SPD
-#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
 
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
@@ -134,14 +142,20 @@
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
 
-/* I2C addresses of SPD EEPROMs */
+/*
+ * The hardware fix for the I2C address collision puts the DDR
+ * SPD at 0x53, but if we are running on an older board w/o the
+ * fix, it will still be at 0x51.  We check 0x53 1st.
+ */
 #define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+#define ALT_SPD_EEPROM_ADDRESS	0x53	/* CTLR 0 DIMM 0 */
 
 /*
  * Make sure required options are set
  */
 #ifndef CONFIG_SPD_EEPROM
 	#define CONFIG_SYS_SDRAM_SIZE	256		/* DDR is 256MB */
+	#define CONFIG_SYS_DDR_CONTROL	0xc300c000
 #endif
 
 #undef CONFIG_CLOCKS_IN_MHZ
@@ -283,6 +297,10 @@
 
 /*
  * SDRAM on the Local Bus (CS3 and CS4)
+ * Note that most boards have a hardware errata where both the
+ * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
+ * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
+ * A hardware workaround is also available, see README.sbc8548 file.
  */
 #define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
 #define CONFIG_SYS_LBC_SDRAM_SIZE	128		/* LBC SDRAM is 128MB */
@@ -416,9 +434,6 @@
 
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
-#ifdef	CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
 
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT		1
@@ -612,19 +627,19 @@
 #define CONFIG_BAUDRATE	115200
 
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
- "netdev=eth0\0"						\
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
- "tftpflash=tftpboot $loadaddr $uboot; "			\
-	"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
-	"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "		\
-	"cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "	\
-	"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "		\
-	"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"	\
- "consoledev=ttyS0\0"				\
- "ramdiskaddr=2000000\0"			\
- "ramdiskfile=uRamdisk\0"			\
- "fdtaddr=c00000\0"				\
- "fdtfile=sbc8548.dtb\0"
+"netdev=eth0\0"						\
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"				\
+"tftpflash=tftpboot $loadaddr $uboot; "			\
+	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
+	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
+	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+"consoledev=ttyS0\0"				\
+"ramdiskaddr=2000000\0"			\
+"ramdiskfile=uRamdisk\0"			\
+"fdtaddr=c00000\0"				\
+"fdtfile=sbc8548.dtb\0"
 
 #define CONFIG_NFSBOOTCOMMAND						\
    "setenv bootargs root=/dev/nfs rw "					\