X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=include%2Fconfigs%2Fsocfpga_common.h;h=6d9347204b225a89a444e6ac84837dc654681efe;hb=d283a5709d8e2bf2682a2e22fb81a47b8d53c111;hp=2b7534b936232ed17a74bc0135e3ca340f4e31ee;hpb=7fb0f596495395f26819e279acef80487360bfea;p=u-boot

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 2b7534b936..6d9347204b 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -19,8 +19,7 @@
  * High level configuration
  */
 #define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_BOARDINFO_LATE
 #define CONFIG_ARCH_EARLY_INIT_R
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_CLOCKS
@@ -139,7 +138,7 @@
 #define CONFIG_DESIGNWARE_WATCHDOG
 #define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
 #define CONFIG_DW_WDT_CLOCK_KHZ		25000
-#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	12000
+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	30000
 #endif
 
 /*
@@ -190,10 +189,6 @@ unsigned int cm_get_l4_sp_clk_hz(void);
  * QSPI support
  */
 #ifdef CONFIG_OF_CONTROL	/* QSPI is controlled via DT */
-#define CONFIG_CMD_DM
-#define CONFIG_DM
-#define CONFIG_DM_SPI
-#define CONFIG_DM_SPI_FLASH
 #define CONFIG_CADENCE_QSPI
 /* Enable multiple SPI NOR flash manufacturers */
 #define CONFIG_SPI_FLASH		/* SPI flash subsystem */
@@ -209,6 +204,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_CMD_SF
 #endif
 
+#ifdef CONFIG_OF_CONTROL	/* DW SPI is controlled via DT */
+#define CONFIG_DESIGNWARE_SPI
+#define CONFIG_CMD_SPI
+#endif
+
 /*
  * Serial Driver
  */