X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=include%2Flcd.h;h=42070d76366e8465a84baf3e90a7e95bff429a62;hb=3f4669334d3bfd795777c18423765210b9180278;hp=3d9ef167107e6f6e1bbfdcd874d6854025b0dae8;hpb=2ab5be7af009b4a40efe2fa5471497c97e70ed28;p=u-boot diff --git a/include/lcd.h b/include/lcd.h index 3d9ef16710..42070d7636 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -55,6 +55,7 @@ extern void lcd_initcolregs (void); /* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */ extern struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp); +extern int bmp_display(ulong addr, int x, int y); #if defined CONFIG_MPC823 /* @@ -157,7 +158,7 @@ typedef struct vidinfo { struct pxafb_info pxa; } vidinfo_t; -#elif defined(CONFIG_ATMEL_LCD) +#elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD) typedef struct vidinfo { ushort vl_col; /* Number of columns (i.e. 640) */ @@ -169,6 +170,7 @@ typedef struct vidinfo { u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ u_long vl_tft; /* 0 = passive, 1 = TFT */ u_long vl_cont_pol_low; /* contrast polarity is low */ + u_long vl_clk_pol; /* clock polarity */ /* Horizontal control register. */ u_long vl_hsync_len; /* Length of horizontal sync */ @@ -190,6 +192,13 @@ enum { FIMD_CPU_INTERFACE = 2, }; +enum exynos_fb_rgb_mode_t { + MODE_RGB_P = 0, + MODE_BGR_P = 1, + MODE_RGB_S = 2, + MODE_BGR_S = 3, +}; + typedef struct vidinfo { ushort vl_col; /* Number of columns (i.e. 640) */ ushort vl_row; /* Number of rows (i.e. 480) */ @@ -231,10 +240,17 @@ typedef struct vidinfo { unsigned int reset_delay; unsigned int interface_mode; unsigned int mipi_enabled; + unsigned int dp_enabled; unsigned int cs_setup; unsigned int wr_setup; unsigned int wr_act; unsigned int wr_hold; + unsigned int logo_on; + unsigned int logo_width; + unsigned int logo_height; + unsigned long logo_addr; + unsigned int rgb_mode; + unsigned int resolution; /* parent clock name(MPLL, EPLL or VPLL) */ unsigned int pclk_name;