X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=it87.c;h=ca687886a7f5258b41caa8631cb19c0976cca2fa;hb=e4056dade6d24caf7e972087d6570236e41d7049;hp=2acc57b73b2ed5adcfe3d7225dc6a21513a63978;hpb=f8240ebfd5429d8a2811b502f884ee6986762166;p=groeck-it87 diff --git a/it87.c b/it87.c index 2acc57b..ca68788 100644 --- a/it87.c +++ b/it87.c @@ -31,6 +31,8 @@ * IT8726F Super I/O chip w/LPC interface * IT8728F Super I/O chip w/LPC interface * IT8732F Super I/O chip w/LPC interface + * IT8736F Super I/O chip w/LPC interface + * IT8738E Super I/O chip w/LPC interface * IT8758E Super I/O chip w/LPC interface * IT8771E Super I/O chip w/LPC interface * IT8772E Super I/O chip w/LPC interface @@ -83,6 +85,7 @@ #define DRVNAME "it87" enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732, + it8736, it8738, it8771, it8772, it8781, it8782, it8783, it8786, it8790, it8792, it8603, it8606, it8607, it8613, it8620, it8622, it8625, it8628, it8655, it8665, it8686 }; @@ -179,6 +182,8 @@ static inline void superio_exit(int ioreg, bool doexit) #define IT8726F_DEVID 0x8726 #define IT8728F_DEVID 0x8728 #define IT8732F_DEVID 0x8732 +#define IT8736F_DEVID 0x8736 +#define IT8738E_DEVID 0x8738 #define IT8792E_DEVID 0x8733 #define IT8771E_DEVID 0x8771 #define IT8772E_DEVID 0x8772 @@ -258,6 +263,10 @@ static bool fix_pwm_polarity; * Super-I/O configuration space. */ #define IT87_REG_VID 0x0a + +/* Interface Selection register on other chips */ +#define IT87_REG_IFSEL 0x0a + /* * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b * for fan divisors. Later IT8712F revisions must use 16-bit tachometer @@ -462,13 +471,40 @@ static const struct it87_devices it87_devices[] = { .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS - | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF, + | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF | FEAT_SCALING, .num_temp_limit = 3, .num_temp_offset = 3, .num_temp_map = 3, .peci_mask = 0x07, .old_peci_mask = 0x02, /* Actually reports PCH */ }, + [it8736] = { + .name = "it8736", + .model = "IT8736F", + .features = FEAT_16BIT_FANS + | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI + | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS + | FEAT_FANCTL_ONOFF | FEAT_SCALING, + .num_temp_limit = 3, + .num_temp_offset = 3, + .num_temp_map = 3, + .peci_mask = 0x07, + .old_peci_mask = 0x02, /* Actually reports PCH */ + }, + [it8738] = { + .name = "it8738", + .model = "IT8738E", + .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS + | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI + | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL + | FEAT_FANCTL_ONOFF | FEAT_SCALING + | FEAT_AVCC3, + .num_temp_limit = 3, + .num_temp_offset = 3, + .num_temp_map = 3, + .peci_mask = 0x07, + .old_peci_mask = 0x02, + }, [it8771] = { .name = "it8771", .model = "IT8771E", @@ -768,6 +804,7 @@ struct it87_data { u8 old_peci_mask; u8 smbus_bitmap; /* !=0 if SMBus needs to be disabled */ + u8 saved_bank; /* saved bank register value */ u8 ec_special_config; /* EC special config register restore value */ u8 sioaddr; /* SIO port address */ bool doexit; /* true if exit from sio config is ok */ @@ -788,7 +825,6 @@ struct it87_data { const u8 *REG_TEMP_HIGH; unsigned short addr; - const char *name; struct mutex update_lock; char valid; /* !=0 if following fields are valid */ unsigned long last_updated; /* In jiffies */ @@ -959,6 +995,18 @@ static const unsigned int pwm_freq[8] = { 750000, }; +static int _it87_io_read(struct it87_data *data, u16 reg) +{ + outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); + return inb_p(data->addr + IT87_DATA_REG_OFFSET); +} + +static void _it87_io_write(struct it87_data *data, u16 reg, u8 value) +{ + outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); + outb_p(value, data->addr + IT87_DATA_REG_OFFSET); +} + static int smbus_disable(struct it87_data *data) { int err; @@ -971,6 +1019,8 @@ static int smbus_disable(struct it87_data *data) superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG, data->ec_special_config & ~data->smbus_bitmap); superio_exit(data->sioaddr, data->doexit); + if (has_bank_sel(data) && !data->mmio) + data->saved_bank = _it87_io_read(data, IT87_REG_BANK); } return 0; } @@ -980,6 +1030,8 @@ static int smbus_enable(struct it87_data *data) int err; if (data->smbus_bitmap) { + if (has_bank_sel(data) && !data->mmio) + _it87_io_write(data, IT87_REG_BANK, data->saved_bank); err = superio_enter(data->sioaddr); if (err) return err; @@ -992,18 +1044,6 @@ static int smbus_enable(struct it87_data *data) return 0; } -static int _it87_io_read(struct it87_data *data, u16 reg) -{ - outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); - return inb_p(data->addr + IT87_DATA_REG_OFFSET); -} - -static void _it87_io_write(struct it87_data *data, u16 reg, u8 value) -{ - outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); - outb_p(value, data->addr + IT87_DATA_REG_OFFSET); -} - static u8 it87_io_set_bank(struct it87_data *data, u8 bank) { u8 _bank = bank; @@ -1135,15 +1175,19 @@ static void it87_unlock(struct it87_data *data) static struct it87_data *it87_update_device(struct device *dev) { struct it87_data *data = dev_get_drvdata(dev); + struct it87_data *ret = data; int err; int i; - err = it87_lock(data); - if (err) - return ERR_PTR(err); + mutex_lock(&data->update_lock); if (time_after(jiffies, data->last_updated + HZ + HZ / 2) || !data->valid) { + err = smbus_disable(data); + if (err) { + ret = ERR_PTR(err); + goto unlock; + } if (update_vbat) { /* * Cleared after each update, so reenable. Value @@ -1240,9 +1284,11 @@ static struct it87_data *it87_update_device(struct device *dev) } data->last_updated = jiffies; data->valid = 1; + smbus_enable(data); } - it87_unlock(data); - return data; +unlock: + mutex_unlock(&data->update_lock); + return ret; } static ssize_t show_in(struct device *dev, struct device_attribute *attr, @@ -1460,11 +1506,12 @@ static int get_temp_type(struct it87_data *data, int index) if (type) return type; - /* Dectect PECI vs. AMDTSI if possible */ + /* Dectect PECI vs. AMDTSI */ ttype = 6; - if ((has_temp_peci(data, index)) && data->type != it8721) { - extra = data->read(data, 0x98); /* PCH/AMDTSI host status */ - if (extra & BIT(6)) + if ((has_temp_peci(data, index)) || data->type == it8721 || + data->type == it8720) { + extra = data->read(data, IT87_REG_IFSEL); + if ((extra & 0x70) == 0x40) ttype = 5; } @@ -2997,6 +3044,12 @@ static int __init it87_find(int sioaddr, unsigned short *address, case IT8732F_DEVID: sio_data->type = it8732; break; + case IT8736F_DEVID: + sio_data->type = it8736; + break; + case IT8738E_DEVID: + sio_data->type = it8738; + break; case IT8792E_DEVID: sio_data->type = it8792; /* @@ -3368,7 +3421,8 @@ static int __init it87_find(int sioaddr, unsigned short *address, sio_data->beep_pin = superio_inb(sioaddr, IT87_SIO_BEEP_PIN_REG) & 0x3f; - } else if (sio_data->type == it8732) { + } else if (sio_data->type == it8732 || sio_data->type == it8736 || + sio_data->type == it8738) { int reg; superio_select(sioaddr, GPIO); @@ -3390,9 +3444,11 @@ static int __init it87_find(int sioaddr, unsigned short *address, sio_data->skip_fan |= BIT(3); /* Check if AVCC is on VIN3 */ - reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); - if (reg & BIT(0)) - sio_data->internal |= BIT(0); + if (sio_data->type != it8738) { + reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); + if (reg & BIT(0)) + sio_data->internal |= BIT(0); + } sio_data->beep_pin = superio_inb(sioaddr, IT87_SIO_BEEP_PIN_REG) & 0x3f; @@ -3430,15 +3486,9 @@ static int __init it87_find(int sioaddr, unsigned short *address, reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG); regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG); - /* Check for pwm2, fan2 */ + /* Check for pwm2 */ if (reg29 & BIT(1)) sio_data->skip_pwm |= BIT(1); - /* - * Note: Table 6-1 in datasheet claims that FAN_TAC2 - * would be enabled with 29h[2]=0. - */ - if (reg2d & BIT(4)) - sio_data->skip_fan |= BIT(1); /* Check for pwm3, fan3 */ if (reg27 & BIT(6)) @@ -3446,28 +3496,38 @@ static int __init it87_find(int sioaddr, unsigned short *address, if (reg27 & BIT(7)) sio_data->skip_fan |= BIT(2); - /* Check for pwm4, fan4, pwm5, fan5 */ + /* Check for fan2, pwm4, fan4, pwm5, fan5 */ if (sio_data->type == it8625) { int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); + if (reg29 & BIT(2)) + sio_data->skip_fan |= BIT(1); if (reg25 & BIT(6)) sio_data->skip_fan |= BIT(3); if (reg25 & BIT(5)) sio_data->skip_pwm |= BIT(3); if (reg27 & BIT(3)) sio_data->skip_pwm |= BIT(4); - if (reg27 & BIT(1)) + if (!(reg27 & BIT(1))) sio_data->skip_fan |= BIT(4); } else { int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); + if (reg2d & BIT(4)) + sio_data->skip_fan |= BIT(1); if (regd3 & BIT(2)) sio_data->skip_pwm |= BIT(3); if (regd3 & BIT(3)) sio_data->skip_fan |= BIT(3); if (reg26 & BIT(5)) sio_data->skip_pwm |= BIT(4); - if (reg26 & BIT(4)) + /* + * Table 6-1 in datasheet claims that FAN_TAC5 would + * be enabled with 26h[4]=0. This contradicts with the + * information in section 8.3.9 and with feedback from + * users. + */ + if (!(reg26 & BIT(4))) sio_data->skip_fan |= BIT(4); } @@ -3939,6 +3999,17 @@ static int it87_probe(struct platform_device *pdev) /* Initialize register pointers */ it87_init_regs(pdev); + /* + * We need to disable SMBus before we can read any registers in + * the envmon address space, even if it is for chip identification + * purposes. If the chip has SMBus client support, it likely also has + * multi-page envmon registers, so we have to set the page anyway + * before accessing those registers. Kind of a chicken-and-egg + * problem. + * Fortunately, the chip was already identified through the SIO + * address space, only recent chips are affected, and this is just + * an additional safeguard. + */ err = smbus_disable(data); if (err) return err; @@ -4242,6 +4313,7 @@ module_param(fix_pwm_polarity, bool, 0000); MODULE_PARM_DESC(fix_pwm_polarity, "Force PWM polarity to active high (DANGEROUS)"); MODULE_LICENSE("GPL"); +MODULE_VERSION(IT87_DRIVER_VERSION); module_init(sm_it87_init); module_exit(sm_it87_exit);