X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=post%2Fcpu%2Fppc4xx%2Ffpu.c;h=e9b96dde8d22acdb58df522ea48fa053c3828509;hb=3cbcfa70b116df1bbdc90ba31c61adcaec058a8a;hp=27e9ed01afc86bc29efe5d7fdd25023e191a56e6;hpb=fd3635190bee477dd19b87da80136c00f11444c0;p=u-boot

diff --git a/post/cpu/ppc4xx/fpu.c b/post/cpu/ppc4xx/fpu.c
index 27e9ed01af..e9b96dde8d 100644
--- a/post/cpu/ppc4xx/fpu.c
+++ b/post/cpu/ppc4xx/fpu.c
@@ -25,17 +25,16 @@
 
 #include <config.h>
 
-#ifdef CONFIG_POST
 #if defined(CONFIG_440EP) || \
     defined(CONFIG_440EPX)
 
-#include <ppc4xx.h>
 #include <asm/processor.h>
+#include <ppc4xx.h>
 
 
 int fpu_status(void)
 {
-	if (mfspr(ccr0) & CCR0_DAPUIB)
+	if (mfspr(SPRN_CCR0) & CCR0_DAPUIB)
 		return 0; /* Disabled */
 	else
 		return 1; /* Enabled */
@@ -44,16 +43,15 @@ int fpu_status(void)
 
 void fpu_disable(void)
 {
-	mtspr(ccr0, mfspr(ccr0) | CCR0_DAPUIB);
+	mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) | CCR0_DAPUIB);
 	mtmsr(mfmsr() & ~MSR_FP);
 }
 
 
 void fpu_enable(void)
 {
-	mtspr(ccr0, mfspr(ccr0) & ~CCR0_DAPUIB);
+	mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) & ~CCR0_DAPUIB);
 	mtmsr(mfmsr() | MSR_FP);
 }
 
 #endif
-#endif /* CONFIG_POST */