X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=post%2Flib_ppc%2Fcmpi.c;h=1a2fc3d094bd5ff70d9d796f84d8c5b04253f693;hb=7f625fc6d3ba8f890e843ac01717804c2462ed53;hp=e0c2aaff8262d38213cf60ba8f9143254512d0da;hpb=d8be57669b37d57625bbe37c4603dab05058cea7;p=u-boot

diff --git a/post/lib_ppc/cmpi.c b/post/lib_ppc/cmpi.c
index e0c2aaff82..1a2fc3d094 100644
--- a/post/lib_ppc/cmpi.c
+++ b/post/lib_ppc/cmpi.c
@@ -36,12 +36,10 @@
  * the result in and the expected result.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include "cpu_asm.h"
 
-#if CONFIG_POST & CFG_POST_CPU
+#if CONFIG_POST & CONFIG_SYS_POST_CPU
 
 extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1);
 
@@ -104,11 +102,12 @@ int cpu_post_test_cmpi (void)
 {
     int ret = 0;
     unsigned int i;
+    int flag = disable_interrupts();
 
     for (i = 0; i < cpu_post_cmpi_size && ret == 0; i++)
     {
 	struct cpu_post_cmpi_s *test = cpu_post_cmpi_table + i;
-    	unsigned long code[] =
+	unsigned long code[] =
 	{
 	    ASM_1IC(test->cmd, test->cr, 3, test->op2),
 	    ASM_MFCR(3),
@@ -126,8 +125,10 @@ int cpu_post_test_cmpi (void)
 	}
     }
 
+    if (flag)
+	enable_interrupts();
+
     return ret;
 }
 
 #endif
-#endif