X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=src%2Ftarget%2Farmv7a.h;h=5ca4eb86ef079390e649f899868e9f2f98cb0567;hb=bfb02d5ba1238bb88cdf28863492cf1521ab2bab;hp=4341acae414208435b32c980ea078642327714ed;hpb=e519099ab7fac4517eaee7dde3275e7b839460ff;p=openocd

diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 4341acae..5ca4eb86 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -21,6 +21,7 @@
 #define ARMV7A_H
 
 #include "arm_adi_v5.h"
+#include "armv7a_cache.h"
 #include "arm.h"
 #include "armv4_5_mmu.h"
 #include "armv4_5_cache.h"
@@ -62,25 +63,35 @@ struct armv7a_cachesize {
 	uint32_t way_shift;
 };
 
-struct armv7a_cache_common {
-	int ctype;
+/* information about one architecture cache at any level */
+struct armv7a_arch_cache {
+	int ctype;				/* cache type, CLIDR encoding */
 	struct armv7a_cachesize d_u_size;	/* data cache */
 	struct armv7a_cachesize i_size;		/* instruction cache */
+};
+
+/* common cache information */
+struct armv7a_cache_common {
+	int info;				/* -1 invalid, else valid */
+	int loc;				/* level of coherency */
+	uint32_t dminline;			/* minimum d-cache linelen */
+	uint32_t iminline;			/* minimum i-cache linelen */
+	struct armv7a_arch_cache arch[6];	/* cache info, L1 - L7 */
 	int i_cache_enabled;
 	int d_u_cache_enabled;
-	/* l2 external unified cache if some */
-	void *l2_cache;
+	int auto_cache_enabled;			/* openocd automatic
+						 * cache handling */
+	/* outer unified cache if some */
+	void *outer_cache;
 	int (*flush_all_data_cache)(struct target *target);
-	int (*display_cache_info)(struct command_context *cmd_ctx,
-			struct armv7a_cache_common *armv7a_cache);
 };
 
 struct armv7a_mmu_common {
 	/* following field mmu working way */
-	int32_t ttbr0_used;
-	int32_t ttbr1_used; /*  -1 not initialized, 0 no ttbr1 1 ttbr1 used and  */
-	uint32_t ttbr0_mask;/*  masked to be used  */
-	uint32_t os_border;
+	int32_t cached;     /* 0: not initialized, 1: initialized */
+	uint32_t ttbcr;     /* cache for ttbcr register */
+	uint32_t ttbr_mask[2];
+	uint32_t ttbr_range[2];
 
 	int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size,
 			uint32_t count, uint8_t *buffer);
@@ -93,13 +104,11 @@ struct armv7a_common {
 	int common_magic;
 	struct reg_cache *core_cache;
 
-	struct adiv5_dap dap;
-
 	/* Core Debug Unit */
 	struct arm_dpm dpm;
 	uint32_t debug_base;
-	uint8_t debug_ap;
-	uint8_t memory_ap;
+	struct adiv5_ap *debug_ap;
+	struct adiv5_ap *memory_ap;
 	bool memory_ap_available;
 	/* mdir */
 	uint8_t multi_processor_system;
@@ -160,6 +169,7 @@ target_to_armv7a(struct target *target)
 
 /* See ARMv7a arch spec section C10.7 */
 #define CPUDBG_DSCCR		0x028
+#define CPUDBG_DSMCR		0x02C
 
 /* See ARMv7a arch spec section C10.8 */
 #define CPUDBG_AUTHSTATUS	0xFB8