X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=src%2Ftarget%2Fcortex_m3.c;h=269d2a67ffeebc7104ff442c5302e88dc58fd9a7;hb=3b7c9585db2dd49b48123d50e9e8af7bc527be52;hp=626157431f995a838b1291af900edb87d24a80e6;hpb=ed22097a55b4bde80c64c68693bbde19b29818c5;p=openocd diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index 62615743..269d2a67 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -31,131 +31,117 @@ #include "config.h" #endif +#include "breakpoints.h" #include "cortex_m3.h" #include "target_request.h" #include "target_type.h" #include "arm_disassembler.h" +#include "register.h" +#include "arm_opcodes.h" +#include "arm_semihosting.h" + +/* NOTE: most of this should work fine for the Cortex-M1 and + * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M. + * Some differences: M0/M1 doesn't have FBP remapping or the + * DWT tracing/profiling support. (So the cycle counter will + * not be usable; the other stuff isn't currently used here.) + * + * Although there are some workarounds for errata seen only in r0p0 + * silicon, such old parts are hard to find and thus not much tested + * any longer. + */ -#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0]))) - - -/* cli handling */ -int cortex_m3_register_commands(struct command_context_s *cmd_ctx); -int handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); - /* forward declarations */ -void cortex_m3_enable_breakpoints(struct target_s *target); -void cortex_m3_enable_watchpoints(struct target_s *target); -int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp); -int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int cortex_m3_quit(void); -int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type, uint32_t num, uint32_t *value); -int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type, uint32_t num, uint32_t value); -int cortex_m3_target_request_data(target_t *target, uint32_t size, uint8_t *buffer); -int cortex_m3_examine(struct target_s *target); - -#ifdef ARMV7_GDB_HACKS -extern uint8_t armv7m_gdb_dummy_cpsr_value[]; -extern reg_t armv7m_gdb_dummy_cpsr_reg; -#endif - -target_type_t cortexm3_target = -{ - .name = "cortex_m3", - - .poll = cortex_m3_poll, - .arch_state = armv7m_arch_state, - - .target_request_data = cortex_m3_target_request_data, - - .halt = cortex_m3_halt, - .resume = cortex_m3_resume, - .step = cortex_m3_step, - - .assert_reset = cortex_m3_assert_reset, - .deassert_reset = cortex_m3_deassert_reset, - .soft_reset_halt = cortex_m3_soft_reset_halt, - - .get_gdb_reg_list = armv7m_get_gdb_reg_list, - - .read_memory = cortex_m3_read_memory, - .write_memory = cortex_m3_write_memory, - .bulk_write_memory = cortex_m3_bulk_write_memory, - .checksum_memory = armv7m_checksum_memory, - .blank_check_memory = armv7m_blank_check_memory, - - .run_algorithm = armv7m_run_algorithm, - - .add_breakpoint = cortex_m3_add_breakpoint, - .remove_breakpoint = cortex_m3_remove_breakpoint, - .add_watchpoint = cortex_m3_add_watchpoint, - .remove_watchpoint = cortex_m3_remove_watchpoint, - - .register_commands = cortex_m3_register_commands, - .target_create = cortex_m3_target_create, - .init_target = cortex_m3_init_target, - .examine = cortex_m3_examine, - .quit = cortex_m3_quit -}; - -int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, uint32_t *value, int regnum) +static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint); +static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint); +static void cortex_m3_enable_watchpoints(struct target *target); +static int cortex_m3_store_core_reg_u32(struct target *target, + enum armv7m_regtype type, uint32_t num, uint32_t value); + +static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp, + uint32_t *value, int regnum) { int retval; uint32_t dcrdr; /* because the DCB_DCRDR is used for the emulated dcc channel - * we gave to save/restore the DCB_DCRDR when used */ - - mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); + * we have to save/restore the DCB_DCRDR when used */ - swjdp->trans_mode = TRANS_MODE_COMPOSITE; + retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); + if (retval != ERROR_OK) + return retval; /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */ - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); - dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum); + retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum); + if (retval != ERROR_OK) + return retval; /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */ - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); - dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value); + retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value); + if (retval != ERROR_OK) + return retval; + + retval = dap_run(swjdp); + if (retval != ERROR_OK) + return retval; + + /* restore DCB_DCRDR - this needs to be in a seperate + * transaction otherwise the emulated DCC channel breaks */ + if (retval == ERROR_OK) + retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr); - mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr); - retval = swjdp_transaction_endcheck(swjdp); return retval; } -int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, uint32_t value, int regnum) +static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp, + uint32_t value, int regnum) { int retval; uint32_t dcrdr; /* because the DCB_DCRDR is used for the emulated dcc channel - * we gave to save/restore the DCB_DCRDR when used */ + * we have to save/restore the DCB_DCRDR when used */ - mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); - - swjdp->trans_mode = TRANS_MODE_COMPOSITE; + retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); + if (retval != ERROR_OK) + return retval; /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */ - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); - dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value); + retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value); + // XXX check retval /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */ - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); - dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR); + retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR); + // XXX check retval + + retval = dap_run(swjdp); + + /* restore DCB_DCRDR - this needs to be in a seperate + * transaction otherwise the emulated DCC channel breaks */ + if (retval == ERROR_OK) + retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr); - mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr); - retval = swjdp_transaction_endcheck(swjdp); return retval; } - -int cortex_m3_write_debug_halt_mask(target_t *target, uint32_t mask_on, uint32_t mask_off) +static int cortex_m3_write_debug_halt_mask(struct target *target, + uint32_t mask_on, uint32_t mask_off) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; /* mask off status bits */ cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off); @@ -165,40 +151,54 @@ int cortex_m3_write_debug_halt_mask(target_t *target, uint32_t mask_on, uint32_t return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr); } -int cortex_m3_clear_halt(target_t *target) +static int cortex_m3_clear_halt(struct target *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + int retval; /* clear step if any */ cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP); /* Read Debug Fault Status Register */ - mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); + retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); + if (retval != ERROR_OK) + return retval; + /* Clear Debug Fault Status */ - mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr); + retval = mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr); + if (retval != ERROR_OK) + return retval; LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr); return ERROR_OK; } -int cortex_m3_single_step_core(target_t *target) +static int cortex_m3_single_step_core(struct target *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; uint32_t dhcsr_save; + int retval; /* backup dhcsr reg */ dhcsr_save = cortex_m3->dcb_dhcsr; - /* mask interrupts if not done already */ + /* Mask interrupts before clearing halt, if done already. This avoids + * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing + * HALT can put the core into an unknown state. + */ if (!(cortex_m3->dcb_dhcsr & C_MASKINTS)) - mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN); - mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN); + { + retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, + DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN); + if (retval != ERROR_OK) + return retval; + } + retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, + DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN); + if (retval != ERROR_OK) + return retval; LOG_DEBUG(" "); /* restore dhcsr reg */ @@ -208,101 +208,103 @@ int cortex_m3_single_step_core(target_t *target) return ERROR_OK; } -int cortex_m3_exec_opcode(target_t *target,uint32_t opcode, int len /* MODE, r0_invalue, &r0_outvalue */) -{ - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; - uint32_t savedram; - int retvalue; - - mem_ap_read_u32(swjdp, 0x20000000, &savedram); - mem_ap_write_u32(swjdp, 0x20000000, opcode); - cortexm3_dap_write_coreregister_u32(swjdp, 0x20000000, 15); - cortex_m3_single_step_core(target); - armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid; - retvalue = mem_ap_write_atomic_u32(swjdp, 0x20000000, savedram); - - return retvalue; -} - -#if 0 -/* Enable interrupts */ -int cortex_m3_cpsie(target_t *target, uint32_t IF) -{ - return cortex_m3_exec_opcode(target, ARMV7M_T_CPSIE(IF), 2); -} - -/* Disable interrupts */ -int cortex_m3_cpsid(target_t *target, uint32_t IF) -{ - return cortex_m3_exec_opcode(target, ARMV7M_T_CPSID(IF), 2); -} -#endif - -int cortex_m3_endreset_event(target_t *target) +static int cortex_m3_endreset_event(struct target *target) { int i; + int retval; uint32_t dcb_demcr; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; - cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list; - cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list; - - mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr); + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct armv7m_common *armv7m = &cortex_m3->armv7m; + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list; + struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list; + + /* REVISIT The four debug monitor bits are currently ignored... */ + retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr); + if (retval != ERROR_OK) + return retval; LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr); - /* this regsiter is used for emulated dcc channel */ - mem_ap_write_u32(swjdp, DCB_DCRDR, 0); + /* this register is used for emulated dcc channel */ + retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0); + if (retval != ERROR_OK) + return retval; /* Enable debug requests */ - mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + if (retval != ERROR_OK) + return retval; if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) - mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN); + { + retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN); + if (retval != ERROR_OK) + return retval; + } /* clear any interrupt masking */ cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS); - /* Enable trace and dwt */ - mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR); - /* Monitor bus faults */ - mem_ap_write_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA); + /* Enable features controlled by ITM and DWT blocks, and catch only + * the vectors we were told to pay attention to. + * + * Target firmware is responsible for all fault handling policy + * choices *EXCEPT* explicitly scripted overrides like "vector_catch" + * or manual updates to the NVIC SHCSR and CCR registers. + */ + retval = mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr); + if (retval != ERROR_OK) + return retval; + + /* Paranoia: evidently some (early?) chips don't preserve all the + * debug state (including FBP, DWT, etc) across reset... + */ /* Enable FPB */ - target_write_u32(target, FP_CTRL, 3); + retval = target_write_u32(target, FP_CTRL, 3); + if (retval != ERROR_OK) + return retval; + cortex_m3->fpb_enabled = 1; /* Restore FPB registers */ for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) { - target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value); + retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value); + if (retval != ERROR_OK) + return retval; } /* Restore DWT registers */ for (i = 0; i < cortex_m3->dwt_num_comp; i++) { - target_write_u32(target, dwt_list[i].dwt_comparator_address, dwt_list[i].comp); - target_write_u32(target, dwt_list[i].dwt_comparator_address | 0x4, dwt_list[i].mask); - target_write_u32(target, dwt_list[i].dwt_comparator_address | 0x8, dwt_list[i].function); + retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0, + dwt_list[i].comp); + if (retval != ERROR_OK) + return retval; + retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4, + dwt_list[i].mask); + if (retval != ERROR_OK) + return retval; + retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8, + dwt_list[i].function); + if (retval != ERROR_OK) + return retval; } - swjdp_transaction_endcheck(swjdp); + retval = dap_run(swjdp); + if (retval != ERROR_OK) + return retval; - armv7m_invalidate_core_regs(target); + register_cache_invalidate(cortex_m3->armv7m.core_cache); /* make sure we have latest dhcsr flags */ - mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); - return ERROR_OK; + return retval; } -int cortex_m3_examine_debug_reason(target_t *target) +static int cortex_m3_examine_debug_reason(struct target *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */ /* only check the debug reason if we don't know it already */ @@ -320,48 +322,65 @@ int cortex_m3_examine_debug_reason(target_t *target) target->debug_reason = DBG_REASON_WATCHPOINT; else if (cortex_m3->nvic_dfsr & DFSR_VCATCH) target->debug_reason = DBG_REASON_BREAKPOINT; - else /* EXTERNAL, HALTED, DWTTRAP w/o BKPT */ + else /* EXTERNAL, HALTED */ target->debug_reason = DBG_REASON_UNDEFINED; } return ERROR_OK; } -int cortex_m3_examine_exception_reason(target_t *target) +static int cortex_m3_examine_exception_reason(struct target *target) { uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1; + struct armv7m_common *armv7m = target_to_armv7m(target); + struct adiv5_dap *swjdp = &armv7m->dap; + int retval; - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; - - mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr); + retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr); + if (retval != ERROR_OK) + return retval; switch (armv7m->exception_number) { case 2: /* NMI */ break; case 3: /* Hard Fault */ - mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr); + retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr); + if (retval != ERROR_OK) + return retval; if (except_sr & 0x40000000) { - mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr); + retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr); + if (retval != ERROR_OK) + return retval; } break; case 4: /* Memory Management */ - mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr); - mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar); + retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar); + if (retval != ERROR_OK) + return retval; break; case 5: /* Bus Fault */ - mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr); - mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar); + retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar); + if (retval != ERROR_OK) + return retval; break; case 6: /* Usage Fault */ - mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr); + retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr); + if (retval != ERROR_OK) + return retval; break; case 11: /* SVCall */ break; case 12: /* Debug Monitor */ - mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr); + retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr); + if (retval != ERROR_OK) + return retval; break; case 14: /* PendSV */ break; @@ -371,29 +390,50 @@ int cortex_m3_examine_exception_reason(target_t *target) except_sr = 0; break; } - swjdp_transaction_endcheck(swjdp); - LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \ - shcsr, except_sr, cfsr, except_ar); - return ERROR_OK; + retval = dap_run(swjdp); + if (retval == ERROR_OK) + LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 + ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32, + armv7m_exception_string(armv7m->exception_number), + shcsr, except_sr, cfsr, except_ar); + return retval; } -int cortex_m3_debug_entry(target_t *target) +/* PSP is used in some thread modes */ +static const int armv7m_psp_reg_map[17] = { + ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3, + ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7, + ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11, + ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC, + ARMV7M_xPSR, +}; + +/* MSP is used in handler and some thread modes */ +static const int armv7m_msp_reg_map[17] = { + ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3, + ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7, + ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11, + ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC, + ARMV7M_xPSR, +}; + +static int cortex_m3_debug_entry(struct target *target) { int i; uint32_t xPSR; int retval; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct armv7m_common *armv7m = &cortex_m3->armv7m; + struct arm *arm = &armv7m->arm; + struct adiv5_dap *swjdp = &armv7m->dap; + struct reg *r; LOG_DEBUG(" "); - if (armv7m->pre_debug_entry) - armv7m->pre_debug_entry(target); cortex_m3_clear_halt(target); - mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + if (retval != ERROR_OK) + return retval; if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK) return retval; @@ -408,20 +448,24 @@ int cortex_m3_debug_entry(target_t *target) armv7m->read_core_reg(target, i); } - xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32); + r = armv7m->core_cache->reg_list + ARMV7M_xPSR; + xPSR = buf_get_u32(r->value, 0, 32); #ifdef ARMV7_GDB_HACKS + /* FIXME this breaks on scan chains with more than one Cortex-M3. + * Instead, each CM3 should have its own dummy value... + */ /* copy real xpsr reg for gdb, setting thumb bit */ buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR); buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1); - armv7m_gdb_dummy_cpsr_reg.valid = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid; - armv7m_gdb_dummy_cpsr_reg.dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty; + armv7m_gdb_dummy_cpsr_reg.valid = r->valid; + armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty; #endif /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */ if (xPSR & 0xf00) { - armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid; + r->dirty = r->valid; cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff); } @@ -430,10 +474,27 @@ int cortex_m3_debug_entry(target_t *target) { armv7m->core_mode = ARMV7M_MODE_HANDLER; armv7m->exception_number = (xPSR & 0x1FF); + + arm->core_mode = ARM_MODE_HANDLER; + arm->map = armv7m_msp_reg_map; } else { - armv7m->core_mode = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1); + unsigned control = buf_get_u32(armv7m->core_cache + ->reg_list[ARMV7M_CONTROL].value, 0, 2); + + /* is this thread privileged? */ + armv7m->core_mode = control & 1; + arm->core_mode = armv7m->core_mode + ? ARM_MODE_USER_THREAD + : ARM_MODE_THREAD; + + /* which stack is it using? */ + if (control & 2) + arm->map = armv7m_psp_reg_map; + else + arm->map = armv7m_msp_reg_map; + armv7m->exception_number = 0; } @@ -444,24 +505,26 @@ int cortex_m3_debug_entry(target_t *target) LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s", armv7m_mode_strings[armv7m->core_mode], - *(uint32_t*)(armv7m->core_cache->reg_list[15].value), + *(uint32_t*)(arm->pc->value), target_state_name(target)); if (armv7m->post_debug_entry) - armv7m->post_debug_entry(target); + { + retval = armv7m->post_debug_entry(target); + if (retval != ERROR_OK) + return retval; + } return ERROR_OK; } -int cortex_m3_poll(target_t *target) +static int cortex_m3_poll(struct target *target) { - int retval; + int detected_failure = ERROR_OK; + int retval = ERROR_OK; enum target_state prev_target_state = target->state; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; /* Read from Debug Halting Control and Status Register */ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); @@ -471,10 +534,32 @@ int cortex_m3_poll(target_t *target) return retval; } + /* Recover from lockup. See ARMv7-M architecture spec, + * section B1.5.15 "Unrecoverable exception cases". + */ + if (cortex_m3->dcb_dhcsr & S_LOCKUP) { + LOG_ERROR("%s -- clearing lockup after double fault", + target_name(target)); + cortex_m3_write_debug_halt_mask(target, C_HALT, 0); + target->debug_reason = DBG_REASON_DBGRQ; + + /* We have to execute the rest (the "finally" equivalent, but + * still throw this exception again). + */ + detected_failure = ERROR_FAIL; + + /* refresh status bits */ + retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + if (retval != ERROR_OK) + return retval; + } + if (cortex_m3->dcb_dhcsr & S_RESET_ST) { /* check if still in reset */ - mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + if (retval != ERROR_OK) + return retval; if (cortex_m3->dcb_dhcsr & S_RESET_ST) { @@ -485,8 +570,11 @@ int cortex_m3_poll(target_t *target) if (target->state == TARGET_RESET) { - /* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */ - LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32 "", cortex_m3->dcb_dhcsr); + /* Cannot switch context while running so endreset is + * called with target->state == TARGET_RESET + */ + LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32, + cortex_m3->dcb_dhcsr); cortex_m3_endreset_event(target); target->state = TARGET_RUNNING; prev_target_state = TARGET_RUNNING; @@ -501,6 +589,9 @@ int cortex_m3_poll(target_t *target) if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK) return retval; + if (arm_semihosting(target, &retval) != 0) + return retval; + target_call_event_callbacks(target, TARGET_EVENT_HALTED); } if (prev_target_state == TARGET_DEBUG_RUNNING) @@ -523,14 +614,17 @@ int cortex_m3_poll(target_t *target) if (cortex_m3->dcb_dhcsr & S_RETIRE_ST) { target->state = TARGET_RUNNING; - return ERROR_OK; + retval = ERROR_OK; } } - return ERROR_OK; + /* Did we detect a failure condition that we cleared? */ + if (detected_failure != ERROR_OK) + retval = detected_failure; + return retval; } -int cortex_m3_halt(target_t *target) +static int cortex_m3_halt(struct target *target) { LOG_DEBUG("target->state: %s", target_state_name(target)); @@ -572,39 +666,53 @@ int cortex_m3_halt(target_t *target) return ERROR_OK; } -int cortex_m3_soft_reset_halt(struct target_s *target) +static int cortex_m3_soft_reset_halt(struct target *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; uint32_t dcb_dhcsr = 0; int retval, timeout = 0; - /* Enter debug state on reset, cf. end_reset_event() */ - mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET); + /* Enter debug state on reset; restore DEMCR in endreset_event() */ + retval = mem_ap_write_u32(swjdp, DCB_DEMCR, + TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET); + if (retval != ERROR_OK) + return retval; - /* Request a reset */ - mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET); + /* Request a core-only reset */ + retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, + AIRCR_VECTKEY | AIRCR_VECTRESET); + if (retval != ERROR_OK) + return retval; target->state = TARGET_RESET; /* registers are now invalid */ - armv7m_invalidate_core_regs(target); + register_cache_invalidate(cortex_m3->armv7m.core_cache); while (timeout < 100) { retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr); if (retval == ERROR_OK) { - mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); - if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH)) + retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, + &cortex_m3->nvic_dfsr); + if (retval != ERROR_OK) + return retval; + if ((dcb_dhcsr & S_HALT) + && (cortex_m3->nvic_dfsr & DFSR_VCATCH)) { - LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%" PRIx32 ", nvic_dfsr 0x%" PRIx32 "", dcb_dhcsr, cortex_m3->nvic_dfsr); + LOG_DEBUG("system reset-halted, DHCSR 0x%08x, " + "DFSR 0x%08x", + (unsigned) dcb_dhcsr, + (unsigned) cortex_m3->nvic_dfsr); cortex_m3_poll(target); + /* FIXME restore user's vector catch config */ return ERROR_OK; } else - LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%" PRIx32 ", %i ms", dcb_dhcsr, timeout); + LOG_DEBUG("waiting for system reset-halt, " + "DHCSR 0x%08x, %d ms", + (unsigned) dcb_dhcsr, timeout); } timeout++; alive_sleep(1); @@ -613,12 +721,26 @@ int cortex_m3_soft_reset_halt(struct target_s *target) return ERROR_OK; } -int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) +static void cortex_m3_enable_breakpoints(struct target *target) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - breakpoint_t *breakpoint = NULL; + struct breakpoint *breakpoint = target->breakpoints; + + /* set any pending breakpoints */ + while (breakpoint) + { + if (!breakpoint->set) + cortex_m3_set_breakpoint(target, breakpoint); + breakpoint = breakpoint->next; + } +} + +static int cortex_m3_resume(struct target *target, int current, + uint32_t address, int handle_breakpoints, int debug_execution) +{ + struct armv7m_common *armv7m = target_to_armv7m(target); + struct breakpoint *breakpoint = NULL; uint32_t resume_pc; + struct reg *r; if (target->state != TARGET_HALTED) { @@ -635,30 +757,50 @@ int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int if (debug_execution) { + r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK; + /* Disable interrupts */ - /* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS, - * This is probably the same issue as Cortex-M3 Errata 377493: - * C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */ - buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1); - armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1; - armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1; + /* We disable interrupts in the PRIMASK register instead of + * masking with C_MASKINTS. This is probably the same issue + * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS + * in parallel with disabled interrupts can cause local faults + * to not be taken. + * + * REVISIT this clearly breaks non-debug execution, since the + * PRIMASK register state isn't saved/restored... workaround + * by never resuming app code after debug execution. + */ + buf_set_u32(r->value, 0, 1, 1); + r->dirty = true; + r->valid = true; /* Make sure we are in Thumb mode */ - buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32, - buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24)); - armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1; - armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1; + r = armv7m->core_cache->reg_list + ARMV7M_xPSR; + buf_set_u32(r->value, 24, 1, 1); + r->dirty = true; + r->valid = true; } /* current = 1: continue on current pc, otherwise continue at
*/ + r = armv7m->arm.pc; if (!current) { - buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32, address); - armv7m->core_cache->reg_list[15].dirty = 1; - armv7m->core_cache->reg_list[15].valid = 1; + buf_set_u32(r->value, 0, 32, address); + r->dirty = true; + r->valid = true; + } + + /* if we halted last time due to a bkpt instruction + * then we have to manually step over it, otherwise + * the core will break again */ + + if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32)) + && !debug_execution) + { + armv7m_maybe_skip_bkpt_inst(target, NULL); } - resume_pc = buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32); + resume_pc = buf_get_u32(r->value, 0, 32); armv7m_restore_context(target); @@ -668,9 +810,9 @@ int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int /* Single step past breakpoint at current address */ if ((breakpoint = breakpoint_find(target, resume_pc))) { - LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)", + LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)", breakpoint->address, - breakpoint->unique_id ); + breakpoint->unique_id); cortex_m3_unset_breakpoint(target, breakpoint); cortex_m3_single_step_core(target); cortex_m3_set_breakpoint(target, breakpoint); @@ -683,7 +825,8 @@ int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int target->debug_reason = DBG_REASON_NOTHALTED; /* registers are now invalid */ - armv7m_invalidate_core_regs(target); + register_cache_invalidate(armv7m->core_cache); + if (!debug_execution) { target->state = TARGET_RUNNING; @@ -701,13 +844,15 @@ int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int } /* int irqstepcount = 0; */ -int cortex_m3_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) +static int cortex_m3_step(struct target *target, int current, + uint32_t address, int handle_breakpoints) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; - breakpoint_t *breakpoint = NULL; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct armv7m_common *armv7m = &cortex_m3->armv7m; + struct adiv5_dap *swjdp = &armv7m->dap; + struct breakpoint *breakpoint = NULL; + struct reg *pc = armv7m->arm.pc; + bool bkpt_inst_found = false; if (target->state != TARGET_HALTED) { @@ -717,12 +862,17 @@ int cortex_m3_step(struct target_s *target, int current, uint32_t address, int h /* current = 1: continue on current pc, otherwise continue at */ if (!current) - buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32, address); + buf_set_u32(pc->value, 0, 32, address); /* the front-end may request us not to handle breakpoints */ - if (handle_breakpoints) - if ((breakpoint = breakpoint_find(target, buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32)))) + if (handle_breakpoints) { + breakpoint = breakpoint_find(target, + buf_get_u32(pc->value, 0, 32)); + if (breakpoint) cortex_m3_unset_breakpoint(target, breakpoint); + } + + armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found); target->debug_reason = DBG_REASON_SINGLESTEP; @@ -730,101 +880,111 @@ int cortex_m3_step(struct target_s *target, int current, uint32_t address, int h target_call_event_callbacks(target, TARGET_EVENT_RESUMED); - /* set step and clear halt */ - cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT); - mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + /* if no bkpt instruction is found at pc then we can perform + * a normal step, otherwise we have to manually step over the bkpt + * instruction - as such simulate a step */ + if (bkpt_inst_found == false) + { + /* set step and clear halt */ + cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT); + } + + int retval; + retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + if (retval != ERROR_OK) + return retval; /* registers are now invalid */ - armv7m_invalidate_core_regs(target); + register_cache_invalidate(cortex_m3->armv7m.core_cache); if (breakpoint) cortex_m3_set_breakpoint(target, breakpoint); - LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr); + LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 + " nvic_icsr = 0x%" PRIx32, + cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr); - cortex_m3_debug_entry(target); + retval = cortex_m3_debug_entry(target); + if (retval != ERROR_OK) + return retval; target_call_event_callbacks(target, TARGET_EVENT_HALTED); - LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr); + LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 + " nvic_icsr = 0x%" PRIx32, + cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr); + return ERROR_OK; } -int cortex_m3_assert_reset(target_t *target) +static int cortex_m3_assert_reset(struct target *target) { - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; - int assert_srst = 1; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; + enum cortex_m3_soft_reset_config reset_config = cortex_m3->soft_reset_config; LOG_DEBUG("target->state: %s", target_state_name(target)); enum reset_types jtag_reset_config = jtag_get_reset_config(); - if (!(jtag_reset_config & RESET_HAS_SRST)) - { - LOG_ERROR("Can't assert SRST"); - return ERROR_FAIL; + + if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) { + /* allow scripts to override the reset event */ + + target_handle_event(target, TARGET_EVENT_RESET_ASSERT); + register_cache_invalidate(cortex_m3->armv7m.core_cache); + target->state = TARGET_RESET; + + return ERROR_OK; } /* Enable debug requests */ - mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + int retval; + retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); + if (retval != ERROR_OK) + return retval; if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) - mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN); + { + retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN); + if (retval != ERROR_OK) + return retval; + } - mem_ap_write_u32(swjdp, DCB_DCRDR, 0); + retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0); + if (retval != ERROR_OK) + return retval; if (!target->reset_halt) { /* Set/Clear C_MASKINTS in a separate operation */ if (cortex_m3->dcb_dhcsr & C_MASKINTS) - mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT); + { + retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, + DBGKEY | C_DEBUGEN | C_HALT); + if (retval != ERROR_OK) + return retval; + } /* clear any debug flags before resuming */ cortex_m3_clear_halt(target); /* clear C_HALT in dhcsr reg */ cortex_m3_write_debug_halt_mask(target, 0, C_HALT); - - /* Enter debug state on reset, cf. end_reset_event() */ - mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR); } else { - /* Enter debug state on reset, cf. end_reset_event() */ - mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET); - } - - /* following hack is to handle luminary reset - * when srst is asserted the luminary device seesm to also clear the debug registers - * which does not match the armv7 debug TRM */ - - if (strcmp(target->variant, "lm3s") == 0) - { - /* get revision of lm3s target, only early silicon has this issue - * Fury Rev B, DustDevil Rev B, Tempest all ok */ - - uint32_t did0; - - if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK) - { - switch ((did0 >> 16) & 0xff) - { - case 0: - /* all Sandstorm suffer issue */ - assert_srst = 0; - break; - - case 1: - case 3: - /* only Fury/DustDevil rev A suffer reset problems */ - if (((did0 >> 8) & 0xff) == 0) - assert_srst = 0; - break; - } - } + /* Halt in debug on reset; endreset_event() restores DEMCR. + * + * REVISIT catching BUSERR presumably helps to defend against + * bad vector table entries. Should this include MMERR or + * other flags too? + */ + retval = mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, + TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET); + if (retval != ERROR_OK) + return retval; } - if (assert_srst) + if (jtag_reset_config & RESET_HAS_SRST) { /* default to asserting srst */ if (jtag_reset_config & RESET_SRST_PULLS_TRST) @@ -838,26 +998,44 @@ int cortex_m3_assert_reset(target_t *target) } else { - /* this causes the luminary device to reset using the watchdog */ - mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ); - LOG_DEBUG("Using Luminary Reset: SYSRESETREQ"); + /* Use a standard Cortex-M3 software reset mechanism. + * We default to using VECRESET as it is supported on all current cores. + * This has the disadvantage of not resetting the peripherals, so a + * reset-init event handler is needed to perform any peripheral resets. + */ + retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, + AIRCR_VECTKEY | ((reset_config == CORTEX_M3_RESET_SYSRESETREQ) + ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET)); + if (retval != ERROR_OK) + return retval; + + LOG_DEBUG("Using Cortex-M3 %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ) + ? "SYSRESETREQ" : "VECTRESET"); + + if (reset_config == CORTEX_M3_RESET_VECTRESET) { + LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event " + "handler to reset any peripherals"); + } { - /* I do not know why this is necessary, but it fixes strange effects - * (step/resume cause a NMI after reset) on LM3S6918 -- Michael Schwingen */ + /* I do not know why this is necessary, but it + * fixes strange effects (step/resume cause NMI + * after reset) on LM3S6918 -- Michael Schwingen + */ uint32_t tmp; - mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp); + retval = mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp); + if (retval != ERROR_OK) + return retval; } } target->state = TARGET_RESET; jtag_add_sleep(50000); - armv7m_invalidate_core_regs(target); + register_cache_invalidate(cortex_m3->armv7m.core_cache); if (target->reset_halt) { - int retval; if ((retval = target_halt(target)) != ERROR_OK) return retval; } @@ -865,7 +1043,7 @@ int cortex_m3_assert_reset(target_t *target) return ERROR_OK; } -int cortex_m3_deassert_reset(target_t *target) +static int cortex_m3_deassert_reset(struct target *target) { LOG_DEBUG("target->state: %s", target_state_name(target)); @@ -876,30 +1054,14 @@ int cortex_m3_deassert_reset(target_t *target) return ERROR_OK; } -void cortex_m3_enable_breakpoints(struct target_s *target) -{ - breakpoint_t *breakpoint = target->breakpoints; - - /* set any pending breakpoints */ - while (breakpoint) - { - if (breakpoint->set == 0) - cortex_m3_set_breakpoint(target, breakpoint); - breakpoint = breakpoint->next; - } -} - -int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int +cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval; int fp_num = 0; uint32_t hilo; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - - cortex_m3_fp_comparator_t * comparator_list = cortex_m3->fp_comparator_list; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list; if (breakpoint->set) { @@ -918,9 +1080,8 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) fp_num++; if (fp_num >= cortex_m3->fp_num_code) { - LOG_DEBUG("ERROR Can not find free FP Comparator"); - LOG_WARNING("ERROR Can not find free FP Comparator"); - exit(-1); + LOG_ERROR("Can not find free FPB Comparator!"); + return ERROR_FAIL; } breakpoint->set = fp_num + 1; hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW; @@ -937,19 +1098,28 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) else if (breakpoint->type == BKPT_SOFT) { uint8_t code[4]; - buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11)); - if ((retval = target_read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK) - { + + /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for + * semihosting; don't use that. Otherwise the BKPT + * parameter is arbitrary. + */ + buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11)); + retval = target_read_memory(target, + breakpoint->address & 0xFFFFFFFE, + breakpoint->length, 1, + breakpoint->orig_instr); + if (retval != ERROR_OK) return retval; - } - if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK) - { + retval = target_write_memory(target, + breakpoint->address & 0xFFFFFFFE, + breakpoint->length, 1, + code); + if (retval != ERROR_OK) return retval; - } - breakpoint->set = 0x11; /* Any nice value but 0 */ + breakpoint->set = true; } - LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", + LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", breakpoint->unique_id, (int)(breakpoint->type), breakpoint->address, @@ -959,13 +1129,12 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int +cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval; - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - cortex_m3_fp_comparator_t * comparator_list = cortex_m3->fp_comparator_list; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list; if (!breakpoint->set) { @@ -973,7 +1142,7 @@ int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint return ERROR_OK; } - LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", + LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", breakpoint->unique_id, (int)(breakpoint->type), breakpoint->address, @@ -1010,16 +1179,15 @@ int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint } } } - breakpoint->set = 0; + breakpoint->set = false; return ERROR_OK; } -int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int +cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); if (cortex_m3->auto_bp_type) { @@ -1060,17 +1228,16 @@ int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (breakpoint->type == BKPT_HARD) cortex_m3->fp_code_available--; - cortex_m3_set_breakpoint(target, breakpoint); - return ERROR_OK; + return cortex_m3_set_breakpoint(target, breakpoint); } -int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int +cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + /* REVISIT why check? FBP can be updated with core running ... */ if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); @@ -1093,114 +1260,150 @@ int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin return ERROR_OK; } -int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int +cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint) { int dwt_num = 0; uint32_t mask, temp; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - cortex_m3_dwt_comparator_t * comparator_list = cortex_m3->dwt_comparator_list; - - if (watchpoint->set) - { - LOG_WARNING("watchpoint (%d) already set", watchpoint->unique_id ); - return ERROR_OK; + /* watchpoint params were validated earlier */ + mask = 0; + temp = watchpoint->length; + while (temp) { + temp >>= 1; + mask++; } + mask--; + + /* REVISIT Don't fully trust these "not used" records ... users + * may set up breakpoints by hand, e.g. dual-address data value + * watchpoint using comparator #1; comparator #0 matching cycle + * count; send data trace info through ITM and TPIU; etc + */ + struct cortex_m3_dwt_comparator *comparator; - if (watchpoint->mask == 0xffffffffu) + for (comparator = cortex_m3->dwt_comparator_list; + comparator->used && dwt_num < cortex_m3->dwt_num_comp; + comparator++, dwt_num++) + continue; + if (dwt_num >= cortex_m3->dwt_num_comp) { - while (comparator_list[dwt_num].used && (dwt_num < cortex_m3->dwt_num_comp)) - dwt_num++; - if (dwt_num >= cortex_m3->dwt_num_comp) - { - LOG_DEBUG("ERROR Can not find free DWT Comparator"); - LOG_WARNING("ERROR Can not find free DWT Comparator"); - return -1; - } - watchpoint->set = dwt_num + 1; - mask = 0; - temp = watchpoint->length; - while (temp > 1) - { - temp = temp / 2; - mask++; - } - comparator_list[dwt_num].used = 1; - comparator_list[dwt_num].comp = watchpoint->address; - comparator_list[dwt_num].mask = mask; - comparator_list[dwt_num].function = watchpoint->rw + 5; - target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address, comparator_list[dwt_num].comp); - target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x4, comparator_list[dwt_num].mask); - target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x8, comparator_list[dwt_num].function); - LOG_DEBUG("dwt_num %i 0x%" PRIx32 " 0x%" PRIx32 " 0x%" PRIx32 "", dwt_num, comparator_list[dwt_num].comp, comparator_list[dwt_num].mask, comparator_list[dwt_num].function); + LOG_ERROR("Can not find free DWT Comparator"); + return ERROR_FAIL; } - else - { - /* Move this test to add_watchpoint */ - LOG_WARNING("Cannot watch data values (id: %d)", - watchpoint->unique_id ); - return ERROR_OK; + comparator->used = 1; + watchpoint->set = dwt_num + 1; + + comparator->comp = watchpoint->address; + target_write_u32(target, comparator->dwt_comparator_address + 0, + comparator->comp); + + comparator->mask = mask; + target_write_u32(target, comparator->dwt_comparator_address + 4, + comparator->mask); + + switch (watchpoint->rw) { + case WPT_READ: + comparator->function = 5; + break; + case WPT_WRITE: + comparator->function = 6; + break; + case WPT_ACCESS: + comparator->function = 7; + break; } - LOG_DEBUG("Watchpoint (ID: %d) address: 0x%08" PRIx32 " set=%d ", - watchpoint->unique_id, watchpoint->address, watchpoint->set ); - return ERROR_OK; + target_write_u32(target, comparator->dwt_comparator_address + 8, + comparator->function); + LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x", + watchpoint->unique_id, dwt_num, + (unsigned) comparator->comp, + (unsigned) comparator->mask, + (unsigned) comparator->function); + return ERROR_OK; } -int cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int +cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - cortex_m3_dwt_comparator_t * comparator_list = cortex_m3->dwt_comparator_list; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct cortex_m3_dwt_comparator *comparator; int dwt_num; if (!watchpoint->set) { - LOG_WARNING("watchpoint (wpid: %d) not set", watchpoint->unique_id ); + LOG_WARNING("watchpoint (wpid: %d) not set", + watchpoint->unique_id); return ERROR_OK; } - LOG_DEBUG("Watchpoint (ID: %d) address: 0x%08" PRIx32 " set=%d ", - watchpoint->unique_id, watchpoint->address,watchpoint->set ); - dwt_num = watchpoint->set - 1; + LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear", + watchpoint->unique_id, dwt_num, + (unsigned) watchpoint->address); + if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp)) { LOG_DEBUG("Invalid DWT Comparator number in watchpoint"); return ERROR_OK; } - comparator_list[dwt_num].used = 0; - comparator_list[dwt_num].function = 0; - target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address | 0x8, comparator_list[dwt_num].function); - watchpoint->set = 0; + comparator = cortex_m3->dwt_comparator_list + dwt_num; + comparator->used = 0; + comparator->function = 0; + target_write_u32(target, comparator->dwt_comparator_address + 8, + comparator->function); + + watchpoint->set = false; return ERROR_OK; } -int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int +cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - if (target->state != TARGET_HALTED) + if (cortex_m3->dwt_comp_available < 1) { - LOG_WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; + LOG_DEBUG("no comparators?"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - if (cortex_m3->dwt_comp_available < 1) - { + /* hardware doesn't support data value masking */ + if (watchpoint->mask != ~(uint32_t)0) { + LOG_DEBUG("watchpoint value masks not supported"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4)) - { + /* hardware allows address masks of up to 32K */ + unsigned mask; + + for (mask = 0; mask < 16; mask++) { + if ((1u << mask) == watchpoint->length) + break; + } + if (mask == 16) { + LOG_DEBUG("unsupported watchpoint length"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + if (watchpoint->address & ((1 << mask) - 1)) { + LOG_DEBUG("watchpoint address is unaligned"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + /* Caller doesn't seem to be able to describe watching for data + * values of zero; that flags "no value". + * + * REVISIT This DWT may well be able to watch for specific data + * values. Requires comparator #1 to set DATAVMATCH and match + * the data, and another comparator (DATAVADDR0) matching addr. + */ + if (watchpoint->value) { + LOG_DEBUG("data value watchpoint not YET supported"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -1210,12 +1413,12 @@ int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } -int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int +cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + /* REVISIT why check? DWT can be updated with core running ... */ if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); @@ -1233,25 +1436,25 @@ int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoin return ERROR_OK; } -void cortex_m3_enable_watchpoints(struct target_s *target) +static void cortex_m3_enable_watchpoints(struct target *target) { - watchpoint_t *watchpoint = target->watchpoints; + struct watchpoint *watchpoint = target->watchpoints; /* set any pending watchpoints */ while (watchpoint) { - if (watchpoint->set == 0) + if (!watchpoint->set) cortex_m3_set_watchpoint(target, watchpoint); watchpoint = watchpoint->next; } } -int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t * value) +static int cortex_m3_load_core_reg_u32(struct target *target, + enum armv7m_regtype type, uint32_t num, uint32_t * value) { int retval; - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct armv7m_common *armv7m = target_to_armv7m(target); + struct adiv5_dap *swjdp = &armv7m->dap; /* NOTE: we "know" here that the register identifiers used * in the v7m header match the Cortex-M3 Debug Core Register @@ -1309,14 +1512,13 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ return ERROR_OK; } -int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t value) +static int cortex_m3_store_core_reg_u32(struct target *target, + enum armv7m_regtype type, uint32_t num, uint32_t value) { int retval; uint32_t reg; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct armv7m_common *armv7m = target_to_armv7m(target); + struct adiv5_dap *swjdp = &armv7m->dap; #ifdef ARMV7_GDB_HACKS /* If the LR register is being modified, make sure it will put us @@ -1339,8 +1541,11 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num); if (retval != ERROR_OK) { - LOG_ERROR("JTAG failure %i", retval); - armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid; + struct reg *r; + + LOG_ERROR("JTAG failure"); + r = armv7m->core_cache->reg_list + num; + r->dirty = r->valid; return ERROR_JTAG_DEVICE_ERROR; } LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value); @@ -1387,21 +1592,16 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty return ERROR_OK; } -int cortex_m3_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int cortex_m3_read_memory(struct target *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; - int retval; - - /* sanitize arguments */ - if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer)) - return ERROR_INVALID_ARGUMENTS; + struct armv7m_common *armv7m = target_to_armv7m(target); + struct adiv5_dap *swjdp = &armv7m->dap; + int retval = ERROR_INVALID_ARGUMENTS; /* cortex_m3 handles unaligned memory access */ - - switch (size) - { + if (count && buffer) { + switch (size) { case 4: retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address); break; @@ -1411,27 +1611,21 @@ int cortex_m3_read_memory(struct target_s *target, uint32_t address, uint32_t si case 1: retval = mem_ap_read_buf_u8(swjdp, buffer, count, address); break; - default: - LOG_ERROR("BUG: we shouldn't get here"); - exit(-1); + } } return retval; } -int cortex_m3_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int cortex_m3_write_memory(struct target *target, uint32_t address, + uint32_t size, uint32_t count, const uint8_t *buffer) { - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; - int retval; + struct armv7m_common *armv7m = target_to_armv7m(target); + struct adiv5_dap *swjdp = &armv7m->dap; + int retval = ERROR_INVALID_ARGUMENTS; - /* sanitize arguments */ - if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer)) - return ERROR_INVALID_ARGUMENTS; - - switch (size) - { + if (count && buffer) { + switch (size) { case 4: retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address); break; @@ -1441,40 +1635,174 @@ int cortex_m3_write_memory(struct target_s *target, uint32_t address, uint32_t s case 1: retval = mem_ap_write_buf_u8(swjdp, buffer, count, address); break; - default: - LOG_ERROR("BUG: we shouldn't get here"); - exit(-1); + } } return retval; } -int cortex_m3_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer) +static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address, + uint32_t count, const uint8_t *buffer) { return cortex_m3_write_memory(target, address, 4, count, buffer); } -void cortex_m3_build_reg_cache(target_t *target) +static int cortex_m3_init_target(struct command_context *cmd_ctx, + struct target *target) { armv7m_build_reg_cache(target); + return ERROR_OK; } -int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +/* REVISIT cache valid/dirty bits are unmaintained. We could set "valid" + * on r/w if the core is not running, and clear on resume or reset ... or + * at least, in a post_restore_context() method. + */ + +struct dwt_reg_state { + struct target *target; + uint32_t addr; + uint32_t value; /* scratch/cache */ +}; + +static int cortex_m3_dwt_get_reg(struct reg *reg) { - cortex_m3_build_reg_cache(target); - return ERROR_OK; + struct dwt_reg_state *state = reg->arch_info; + + return target_read_u32(state->target, state->addr, &state->value); +} + +static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf) +{ + struct dwt_reg_state *state = reg->arch_info; + + return target_write_u32(state->target, state->addr, + buf_get_u32(buf, 0, reg->size)); +} + +struct dwt_reg { + uint32_t addr; + char *name; + unsigned size; +}; + +static struct dwt_reg dwt_base_regs[] = { + { DWT_CTRL, "dwt_ctrl", 32, }, + /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly + * increments while the core is asleep. + */ + { DWT_CYCCNT, "dwt_cyccnt", 32, }, + /* plus some 8 bit counters, useful for profiling with TPIU */ +}; + +static struct dwt_reg dwt_comp[] = { +#define DWT_COMPARATOR(i) \ + { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \ + { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \ + { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, } + DWT_COMPARATOR(0), + DWT_COMPARATOR(1), + DWT_COMPARATOR(2), + DWT_COMPARATOR(3), +#undef DWT_COMPARATOR +}; + +static const struct reg_arch_type dwt_reg_type = { + .get = cortex_m3_dwt_get_reg, + .set = cortex_m3_dwt_set_reg, +}; + +static void +cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d) +{ + struct dwt_reg_state *state; + + state = calloc(1, sizeof *state); + if (!state) + return; + state->addr = d->addr; + state->target = t; + + r->name = d->name; + r->size = d->size; + r->value = &state->value; + r->arch_info = state; + r->type = &dwt_reg_type; } -int cortex_m3_examine(struct target_s *target) +static void +cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target) +{ + uint32_t dwtcr; + struct reg_cache *cache; + struct cortex_m3_dwt_comparator *comparator; + int reg, i; + + target_read_u32(target, DWT_CTRL, &dwtcr); + if (!dwtcr) { + LOG_DEBUG("no DWT"); + return; + } + + cm3->dwt_num_comp = (dwtcr >> 28) & 0xF; + cm3->dwt_comp_available = cm3->dwt_num_comp; + cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp, + sizeof(struct cortex_m3_dwt_comparator)); + if (!cm3->dwt_comparator_list) { +fail0: + cm3->dwt_num_comp = 0; + LOG_ERROR("out of mem"); + return; + } + + cache = calloc(1, sizeof *cache); + if (!cache) { +fail1: + free(cm3->dwt_comparator_list); + goto fail0; + } + cache->name = "cortex-m3 dwt registers"; + cache->num_regs = 2 + cm3->dwt_num_comp * 3; + cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list); + if (!cache->reg_list) { + free(cache); + goto fail1; + } + + for (reg = 0; reg < 2; reg++) + cortex_m3_dwt_addreg(target, cache->reg_list + reg, + dwt_base_regs + reg); + + comparator = cm3->dwt_comparator_list; + for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) { + int j; + + comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i; + for (j = 0; j < 3; j++, reg++) + cortex_m3_dwt_addreg(target, cache->reg_list + reg, + dwt_comp + 3 * i + j); + } + + *register_get_last_cache_p(&target->reg_cache) = cache; + cm3->dwt_cache = cache; + + LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s", + dwtcr, cm3->dwt_num_comp, + (dwtcr & (0xf << 24)) ? " only" : "/trigger"); + + /* REVISIT: if num_comp > 1, check whether comparator #1 can + * implement single-address data value watchpoints ... so we + * won't need to check it later, when asked to set one up. + */ +} + +static int cortex_m3_examine(struct target *target) { int retval; - uint32_t cpuid, fpcr, dwtcr, ictr; + uint32_t cpuid, fpcr; int i; - - /* get pointers to arch-specific information */ - armv7m_common_t *armv7m = target->arch_info; - cortex_m3_common_t *cortex_m3 = armv7m->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct cortex_m3_common *cortex_m3 = target_to_cm3(target); + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK) return retval; @@ -1484,21 +1812,16 @@ int cortex_m3_examine(struct target_s *target) target_set_examined(target); /* Read from Device Identification Registers */ - if ((retval = target_read_u32(target, CPUID, &cpuid)) != ERROR_OK) + retval = target_read_u32(target, CPUID, &cpuid); + if (retval != ERROR_OK) return retval; if (((cpuid >> 4) & 0xc3f) == 0xc23) - LOG_DEBUG("CORTEX-M3 processor detected"); + LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected", + (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf)); LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid); - target_read_u32(target, NVIC_ICTR, &ictr); - cortex_m3->intlinesnum = (ictr & 0x1F) + 1; - cortex_m3->intsetenable = calloc(cortex_m3->intlinesnum, 4); - for (i = 0; i < cortex_m3->intlinesnum; i++) - { - target_read_u32(target, NVIC_ISE0 + 4 * i, cortex_m3->intsetenable + i); - LOG_DEBUG("interrupt enable[%i] = 0x%8.8" PRIx32 "", i, cortex_m3->intsetenable[i]); - } + /* NOTE: FPB and DWT are both optional. */ /* Setup FPB */ target_read_u32(target, FP_CTRL, &fpcr); @@ -1506,7 +1829,7 @@ int cortex_m3_examine(struct target_s *target) cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */ cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF; cortex_m3->fp_code_available = cortex_m3->fp_num_code; - cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t)); + cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator)); cortex_m3->fpb_enabled = fpcr & 1; for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) { @@ -1516,28 +1839,22 @@ int cortex_m3_examine(struct target_s *target) LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit); /* Setup DWT */ - target_read_u32(target, DWT_CTRL, &dwtcr); - cortex_m3->dwt_num_comp = (dwtcr >> 28) & 0xF; - cortex_m3->dwt_comp_available = cortex_m3->dwt_num_comp; - cortex_m3->dwt_comparator_list = calloc(cortex_m3->dwt_num_comp, sizeof(cortex_m3_dwt_comparator_t)); - for (i = 0; i < cortex_m3->dwt_num_comp; i++) - { - cortex_m3->dwt_comparator_list[i].dwt_comparator_address = DWT_COMP0 + 0x10 * i; - } - } - - return ERROR_OK; -} + cortex_m3_dwt_setup(cortex_m3, target); -int cortex_m3_quit(void) -{ + /* These hardware breakpoints only work for code in flash! */ + LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints", + target_name(target), + cortex_m3->fp_num_code, + cortex_m3->dwt_num_comp); + } return ERROR_OK; } -int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl) +static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl) { uint16_t dcrdr; + int retval; mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR); *ctrl = (uint8_t)dcrdr; @@ -1550,16 +1867,19 @@ int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl) if (dcrdr & (1 << 0)) { dcrdr = 0; - mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR); + retval = mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR); + if (retval != ERROR_OK) + return retval; } return ERROR_OK; } -int cortex_m3_target_request_data(target_t *target, uint32_t size, uint8_t *buffer) +static int cortex_m3_target_request_data(struct target *target, + uint32_t size, uint8_t *buffer) { - armv7m_common_t *armv7m = target->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct armv7m_common *armv7m = target_to_armv7m(target); + struct adiv5_dap *swjdp = &armv7m->dap; uint8_t data; uint8_t ctrl; uint32_t i; @@ -1573,13 +1893,13 @@ int cortex_m3_target_request_data(target_t *target, uint32_t size, uint8_t *buff return ERROR_OK; } -int cortex_m3_handle_target_request(void *priv) +static int cortex_m3_handle_target_request(void *priv) { - target_t *target = priv; + struct target *target = priv; if (!target_was_examined(target)) return ERROR_OK; - armv7m_common_t *armv7m = target->arch_info; - swjdp_common_t *swjdp = &armv7m->swjdp_info; + struct armv7m_common *armv7m = target_to_armv7m(target); + struct adiv5_dap *swjdp = &armv7m->dap; if (!target->dbg_msg_enabled) return ERROR_OK; @@ -1611,11 +1931,11 @@ int cortex_m3_handle_target_request(void *priv) return ERROR_OK; } -int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap) +static int cortex_m3_init_arch_info(struct target *target, + struct cortex_m3_common *cortex_m3, struct jtag_tap *tap) { int retval; - armv7m_common_t *armv7m; - armv7m = &cortex_m3->armv7m; + struct armv7m_common *armv7m = &cortex_m3->armv7m; armv7m_init_arch_info(target, armv7m); @@ -1623,28 +1943,25 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jt cortex_m3->jtag_info.tap = tap; cortex_m3->jtag_info.scann_size = 4; - armv7m->swjdp_info.dp_select_value = -1; - armv7m->swjdp_info.ap_csw_value = -1; - armv7m->swjdp_info.ap_tar_value = -1; - armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info; - armv7m->swjdp_info.memaccess_tck = 8; - armv7m->swjdp_info.tar_autoincr_block = (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */ + /* default reset mode is to use srst if fitted + * if not it will use CORTEX_M3_RESET_VECTRESET */ + cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET; - /* initialize arch-specific breakpoint handling */ + armv7m->arm.dap = &armv7m->dap; - cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC; - cortex_m3->arch_info = NULL; + /* Leave (only) generic DAP stuff for debugport_init(); */ + armv7m->dap.jtag_info = &cortex_m3->jtag_info; + armv7m->dap.memaccess_tck = 8; + /* Cortex-M3 has 4096 bytes autoincrement range */ + armv7m->dap.tar_autoincr_block = (1 << 12); /* register arch-specific functions */ armv7m->examine_debug_reason = cortex_m3_examine_debug_reason; - armv7m->pre_debug_entry = NULL; armv7m->post_debug_entry = NULL; armv7m->pre_restore_context = NULL; - armv7m->post_restore_context = NULL; - armv7m->arch_info = cortex_m3; armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32; armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32; @@ -1658,56 +1975,34 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jt return ERROR_OK; } -int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp) +static int cortex_m3_target_create(struct target *target, Jim_Interp *interp) { - cortex_m3_common_t *cortex_m3 = calloc(1,sizeof(cortex_m3_common_t)); + struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common)); + cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC; cortex_m3_init_arch_info(target, cortex_m3, target->tap); return ERROR_OK; } -/* - * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well - * as at least ARM-1156T2. The interesting thing about Cortex-M is - * that *only* Thumb2 disassembly matters. There are also some small - * additions to Thumb2 that are specific to ARMv7-M. - */ -static int -handle_cortex_m3_disassemble_command(struct command_context_s *cmd_ctx, - char *cmd, char **args, int argc) -{ - int retval = ERROR_OK; - target_t *target = get_current_target(cmd_ctx); - uint32_t address; - unsigned long count; - arm_instruction_t cur_instruction; - - if (argc != 2) { - command_print(cmd_ctx, - "usage: cortex_m3 disassemble