X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=src%2Ftarget%2Fcortex_m3.h;h=e6714d0077fde554af5453a4692f3e5cc167cbc8;hb=889bd3e7163864e78ab73ed0d340b5fd1e0493e4;hp=9ef8f7a42aef102a48152e674d12c69c1b0b8630;hpb=0cba0d4df3fe120f08945703506f8405760325c9;p=openocd

diff --git a/src/target/cortex_m3.h b/src/target/cortex_m3.h
index 9ef8f7a4..e6714d00 100644
--- a/src/target/cortex_m3.h
+++ b/src/target/cortex_m3.h
@@ -29,7 +29,7 @@
 #include "register.h"
 #include "target.h"
 #include "armv7m.h"
-#include "cortex_swjdp.h"
+//#include "arm_adi_v5.h"
 
 extern char* cortex_m3_state_strings[];
 
@@ -44,7 +44,7 @@ extern char* cortex_m3_state_strings[];
 #define DCB_DCRDR	0xE000EDF8
 #define DCB_DEMCR	0xE000EDFC
 
-#define DCRSR_WnR	(1<<16)	
+#define DCRSR_WnR	(1 << 16)
 
 #define DWT_CTRL	0xE0001000
 #define DWT_COMP0	0xE0001020
@@ -65,23 +65,23 @@ extern char* cortex_m3_state_strings[];
 #define DWT_CTRL	0xE0001000
 
 /* DCB_DHCSR bit and field definitions */
-#define DBGKEY		(0xA05F<<16)
-#define C_DEBUGEN	(1<<0)
-#define C_HALT		(1<<1)
-#define C_STEP		(1<<2)
-#define C_MASKINTS	(1<<3)
-#define S_REGRDY	(1<<16)
-#define S_HALT		(1<<17)
-#define S_SLEEP		(1<<18)
-#define S_LOCKUP	(1<<19)
-#define S_RETIRE_ST	(1<<24)
-#define S_RESET_ST	(1<<25)
+#define DBGKEY		(0xA05F << 16)
+#define C_DEBUGEN	(1 << 0)
+#define C_HALT		(1 << 1)
+#define C_STEP		(1 << 2)
+#define C_MASKINTS	(1 << 3)
+#define S_REGRDY	(1 << 16)
+#define S_HALT		(1 << 17)
+#define S_SLEEP		(1 << 18)
+#define S_LOCKUP	(1 << 19)
+#define S_RETIRE_ST	(1 << 24)
+#define S_RESET_ST	(1 << 25)
 
 /* DCB_DEMCR bit and field definitions */
-#define	TRCENA			(1<<24)
-#define	VC_HARDERR		(1<<10)
-#define	VC_BUSERR		(1<<8)
-#define	VC_CORERESET	(1<<0)
+#define	TRCENA			(1 << 24)
+#define	VC_HARDERR		(1 << 10)
+#define	VC_BUSERR		(1 << 8)
+#define	VC_CORERESET	(1 << 0)
 
 #define NVIC_ICTR		0xE000E004
 #define NVIC_ISE0		0xE000E100
@@ -98,12 +98,12 @@ extern char* cortex_m3_state_strings[];
 #define NVIC_BFAR		0xE000ED38
 
 /* NVIC_AIRCR bits */
-#define AIRCR_VECTKEY		(0x5FA<<16)
-#define AIRCR_SYSRESETREQ	(1<<2)
-#define AIRCR_VECTCLRACTIVE	(1<<1)
-#define AIRCR_VECTRESET		(1<<0)
+#define AIRCR_VECTKEY		(0x5FA << 16)
+#define AIRCR_SYSRESETREQ	(1 << 2)
+#define AIRCR_VECTCLRACTIVE	(1 << 1)
+#define AIRCR_VECTRESET		(1 << 0)
 /* NVIC_SHCSR bits */
-#define SHCSR_BUSFAULTENA	(1<<17)
+#define SHCSR_BUSFAULTENA	(1 << 17)
 /* NVIC_DFSR bits */
 #define DFSR_HALTED			1
 #define DFSR_BKPT			2
@@ -112,38 +112,38 @@ extern char* cortex_m3_state_strings[];
 
 #define FPCR_CODE 0
 #define FPCR_LITERAL 1
-#define FPCR_REPLACE_REMAP  (0<<30)
-#define FPCR_REPLACE_BKPT_LOW  (1<<30)
-#define FPCR_REPLACE_BKPT_HIGH  (2<<30)
-#define FPCR_REPLACE_BKPT_BOTH  (3<<30)
+#define FPCR_REPLACE_REMAP  (0 << 30)
+#define FPCR_REPLACE_BKPT_LOW  (1 << 30)
+#define FPCR_REPLACE_BKPT_HIGH  (2 << 30)
+#define FPCR_REPLACE_BKPT_BOTH  (3 << 30)
 
 typedef struct  cortex_m3_fp_comparator_s
 {
 	int used;
 	int type;
-	u32 fpcr_value;
-	u32 fpcr_address;
+	uint32_t fpcr_value;
+	uint32_t fpcr_address;
 } cortex_m3_fp_comparator_t;
 
 typedef struct  cortex_m3_dwt_comparator_s
 {
 	int used;
-	u32 comp;
-	u32 mask;
-	u32 function;
-	u32 dwt_comparator_address;
+	uint32_t comp;
+	uint32_t mask;
+	uint32_t function;
+	uint32_t dwt_comparator_address;
 } cortex_m3_dwt_comparator_t;
 
 typedef struct cortex_m3_common_s
 {
 	int common_magic;
 	arm_jtag_t jtag_info;
-	
+
 	/* Context information */
-	u32 dcb_dhcsr;
-	u32 nvic_dfsr;  /* Debug Fault Status Register - shows reason for debug halt */
-	u32 nvic_icsr;  /* Interrupt Control State Register - shows active and pending IRQ */
-	
+	uint32_t dcb_dhcsr;
+	uint32_t nvic_dfsr;  /* Debug Fault Status Register - shows reason for debug halt */
+	uint32_t nvic_icsr;  /* Interrupt Control State Register - shows active and pending IRQ */
+
 	/* Flash Patch and Breakpoint (FPB) */
 	int fp_num_lit;
 	int fp_num_code;
@@ -151,18 +151,18 @@ typedef struct cortex_m3_common_s
 	int fpb_enabled;
 	int auto_bp_type;
 	cortex_m3_fp_comparator_t *fp_comparator_list;
-	
+
 	/* Data Watchpoint and Trace (DWT) */
 	int dwt_num_comp;
 	int dwt_comp_available;
 	cortex_m3_dwt_comparator_t *dwt_comparator_list;
-	
+
 	/* Interrupts */
 	int intlinesnum;
-	u32 *intsetenable;
-	
+	uint32_t *intsetenable;
+
 	armv7m_common_t armv7m;
-	swjdp_common_t swjdp_info;
+//	swjdp_common_t swjdp_info;
 	void *arch_info;
 } cortex_m3_common_t;
 
@@ -170,16 +170,16 @@ extern void cortex_m3_build_reg_cache(target_t *target);
 
 int cortex_m3_poll(target_t *target);
 int cortex_m3_halt(target_t *target);
-int cortex_m3_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
-int cortex_m3_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
+int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
+int cortex_m3_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints);
 
 int cortex_m3_assert_reset(target_t *target);
 int cortex_m3_deassert_reset(target_t *target);
 int cortex_m3_soft_reset_halt(struct target_s *target);
 
-int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
-int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
-int cortex_m3_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
+int cortex_m3_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int cortex_m3_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int cortex_m3_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer);
 
 int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
 int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
@@ -188,7 +188,7 @@ int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin
 int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
 
-extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
+//extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
 extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap);
 
 #endif /* CORTEX_M3_H */