X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=src%2Ftarget%2Fetb.h;h=b262841ca22d978f8870129efc8bd481af33571d;hb=c7565cc38177c264306770c1b3714e8477053167;hp=af6e25499f1dcfcfd2a69e61a0b25a5a6bf8d651;hpb=8c1ec4f0e1a7dd37a2549d83b6cd5c8c57eb34aa;p=openocd

diff --git a/src/target/etb.h b/src/target/etb.h
index af6e2549..b262841c 100644
--- a/src/target/etb.h
+++ b/src/target/etb.h
@@ -20,12 +20,6 @@
 #ifndef ETB_H
 #define ETB_H
 
-#include "command.h"
-#include "target.h"
-#include "register.h"
-#include "arm_jtag.h"
-
-#include "etb.h"
 #include "etm.h"
 
 /* ETB registers */
@@ -46,17 +40,17 @@ typedef struct etb_s
 {
 	etm_context_t *etm_ctx;
 	jtag_tap_t *tap;
-	u32 cur_scan_chain;
+	uint32_t cur_scan_chain;
 	reg_cache_t *reg_cache;
-	
+
 	/* ETB parameters */
-	u32 ram_depth;
-	u32 ram_width;
+	uint32_t ram_depth;
+	uint32_t ram_width;
 } etb_t;
 
 typedef struct etb_reg_s
 {
-	u32 addr;
+	uint32_t addr;
 	etb_t *etb;
 } etb_reg_t;
 
@@ -64,10 +58,10 @@ extern etm_capture_driver_t etb_capture_driver;
 
 extern reg_cache_t* etb_build_reg_cache(etb_t *etb);
 extern int etb_read_reg(reg_t *reg);
-extern int etb_write_reg(reg_t *reg, u32 value);
-extern int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask);
+extern int etb_write_reg(reg_t *reg, uint32_t value);
+extern int etb_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask);
 extern int etb_store_reg(reg_t *reg);
-extern int etb_set_reg(reg_t *reg, u32 value);
-extern int etb_set_reg_w_exec(reg_t *reg, u8 *buf);
+extern int etb_set_reg(reg_t *reg, uint32_t value);
+extern int etb_set_reg_w_exec(reg_t *reg, uint8_t *buf);
 
 #endif /* ETB_H */