X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;ds=sidebyside;f=src%2Ftarget%2Fxscale.c;h=40126c92837cf746382be1ac4551eef5c1e21956;hb=efef05870d726fe4cb6786d785fae4628fe7ec1e;hp=3947da0b49974180f1622dbef347e4f1c6596eb7;hpb=c977616cdad17ad74742ede8703f54e370c3947d;p=openocd diff --git a/src/target/xscale.c b/src/target/xscale.c index 3947da0b..40126c92 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -2,9 +2,12 @@ * Copyright (C) 2006, 2007 by Dominic Rath * * Dominic.Rath@gmx.de * * * - * Copyright (C) 2007,2008 Øyvind Harboe * + * Copyright (C) 2007,2008 Ãyvind Harboe * * oyvind.harboe@zylin.com * * * + * Copyright (C) 2009 Michael Schwingen * + * michael@schwingen.org * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -25,6 +28,7 @@ #endif #include "xscale.h" +#include "target_type.h" #include "arm7_9_common.h" #include "arm_simulator.h" #include "arm_disassembler.h" @@ -42,8 +46,8 @@ int xscale_quit(void); int xscale_arch_state(struct target_s *target); int xscale_poll(target_t *target); int xscale_halt(target_t *target); -int xscale_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution); -int xscale_step(struct target_s *target, int current, u32 address, int handle_breakpoints); +int xscale_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution); +int xscale_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints); int xscale_debug_entry(target_t *target); int xscale_restore_context(target_t *target); @@ -51,14 +55,14 @@ int xscale_assert_reset(target_t *target); int xscale_deassert_reset(target_t *target); int xscale_soft_reset_halt(struct target_s *target); -int xscale_set_reg_u32(reg_t *reg, u32 value); +int xscale_set_reg_u32(reg_t *reg, uint32_t value); int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode); -int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value); +int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value); -int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); -int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); -int xscale_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer); +int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); +int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); +int xscale_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer); int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint); int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint); @@ -68,7 +72,7 @@ int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint); int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint); void xscale_enable_watchpoints(struct target_s *target); void xscale_enable_breakpoints(struct target_s *target); -static int xscale_virt2phys(struct target_s *target, u32 virtual, u32 *physical); +static int xscale_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical); static int xscale_mmu(struct target_s *target, int *enabled); int xscale_read_trace(target_t *target); @@ -169,7 +173,7 @@ xscale_reg_t xscale_reg_arch_info[] = int xscale_reg_arch_type = -1; int xscale_get_reg(reg_t *reg); -int xscale_set_reg(reg_t *reg, u8 *buf); +int xscale_set_reg(reg_t *reg, uint8_t *buf); int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xscale_common_t **xscale_p) { @@ -194,9 +198,9 @@ int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xsc return ERROR_OK; } -int xscale_jtag_set_instr(jtag_tap_t *tap, u32 new_instr) +int xscale_jtag_set_instr(jtag_tap_t *tap, uint32_t new_instr) { - if (tap==NULL) + if (tap == NULL) return ERROR_FAIL; if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) @@ -208,10 +212,10 @@ int xscale_jtag_set_instr(jtag_tap_t *tap, u32 new_instr) field.out_value = calloc(CEIL(field.num_bits, 8), 1); buf_set_u32(field.out_value, 0, field.num_bits, new_instr); - u8 tmp[4]; + uint8_t tmp[4]; field.in_value = tmp; - jtag_add_ir_scan(1, &field, TAP_INVALID); + jtag_add_ir_scan(1, &field, jtag_get_end_state()); /* FIX!!!! isn't this check superfluous? verify_ircapture handles this? */ jtag_check_value_mask(&field, tap->expected, tap->expected_mask); @@ -230,14 +234,14 @@ int xscale_read_dcsr(target_t *target) int retval; scan_field_t fields[3]; - u8 field0 = 0x0; - u8 field0_check_value = 0x2; - u8 field0_check_mask = 0x7; - u8 field2 = 0x0; - u8 field2_check_value = 0x0; - u8 field2_check_mask = 0x1; - - jtag_add_end_state(TAP_DRPAUSE); + uint8_t field0 = 0x0; + uint8_t field0_check_value = 0x2; + uint8_t field0_check_mask = 0x7; + uint8_t field2 = 0x0; + uint8_t field2_check_value = 0x0; + uint8_t field2_check_mask = 0x1; + + jtag_set_end_state(TAP_DRPAUSE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); buf_set_u32(&field0, 1, 1, xscale->hold_rst); @@ -246,7 +250,7 @@ int xscale_read_dcsr(target_t *target) fields[0].tap = xscale->jtag_info.tap; fields[0].num_bits = 3; fields[0].out_value = &field0; - u8 tmp; + uint8_t tmp; fields[0].in_value = &tmp; fields[1].tap = xscale->jtag_info.tap; @@ -258,13 +262,13 @@ int xscale_read_dcsr(target_t *target) fields[2].tap = xscale->jtag_info.tap; fields[2].num_bits = 1; fields[2].out_value = &field2; - u8 tmp2; + uint8_t tmp2; fields[2].in_value = &tmp2; - jtag_add_dr_scan(3, fields, TAP_INVALID); + jtag_add_dr_scan(3, fields, jtag_get_end_state()); - jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask); - jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask); + jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask); + jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -282,9 +286,9 @@ int xscale_read_dcsr(target_t *target) fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value; fields[1].in_value = NULL; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); - jtag_add_dr_scan(3, fields, TAP_INVALID); + jtag_add_dr_scan(3, fields, jtag_get_end_state()); /* DANGER!!! this must be here. It will make sure that the arguments * to jtag_set_check_value() does not go out of scope! */ @@ -292,29 +296,30 @@ int xscale_read_dcsr(target_t *target) } -static void xscale_getbuf(u8 *in) +static void xscale_getbuf(jtag_callback_data_t arg) { - *((u32 *)in)=buf_get_u32(in, 0, 32); + uint8_t *in = (uint8_t *)arg; + *((uint32_t *)in) = buf_get_u32(in, 0, 32); } -int xscale_receive(target_t *target, u32 *buffer, int num_words) +int xscale_receive(target_t *target, uint32_t *buffer, int num_words) { - if (num_words==0) + if (num_words == 0) return ERROR_INVALID_ARGUMENTS; - int retval=ERROR_OK; + int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; tap_state_t path[3]; scan_field_t fields[3]; - u8 *field0 = malloc(num_words * 1); - u8 field0_check_value = 0x2; - u8 field0_check_mask = 0x6; - u32 *field1 = malloc(num_words * 4); - u8 field2_check_value = 0x0; - u8 field2_check_mask = 0x1; + uint8_t *field0 = malloc(num_words * 1); + uint8_t field0_check_value = 0x2; + uint8_t field0_check_mask = 0x6; + uint32_t *field1 = malloc(num_words * 4); + uint8_t field2_check_value = 0x0; + uint8_t field2_check_mask = 0x1; int words_done = 0; int words_scheduled = 0; @@ -344,12 +349,12 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) fields[2].check_value = &field2_check_value; fields[2].check_mask = &field2_check_mask; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx); - jtag_add_runtest(1, TAP_INVALID); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */ + jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */ /* repeat until all words have been collected */ - int attempts=0; + int attempts = 0; while (words_done < num_words) { /* schedule reads */ @@ -360,11 +365,11 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) jtag_add_pathmove(3, path); - fields[1].in_value = (u8 *)(field1+i); + fields[1].in_value = (uint8_t *)(field1 + i); - jtag_add_dr_scan_check(3, fields, TAP_IDLE); + jtag_add_dr_scan_check(3, fields, jtag_set_end_state(TAP_IDLE)); - jtag_add_callback(xscale_getbuf, (u8 *)(field1+i)); + jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1 + i)); words_scheduled++; } @@ -384,18 +389,18 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) int j; for (j = i; j < num_words - 1; j++) { - field0[j] = field0[j+1]; - field1[j] = field1[j+1]; + field0[j] = field0[j + 1]; + field1[j] = field1[j + 1]; } words_scheduled--; } } - if (words_scheduled==0) + if (words_scheduled == 0) { if (attempts++==1000) { LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts"); - retval=ERROR_TARGET_TIMEOUT; + retval = ERROR_TARGET_TIMEOUT; break; } } @@ -404,7 +409,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) } for (i = 0; i < num_words; i++) - *(buffer++) = buf_get_u32((u8*)&field1[i], 0, 32); + *(buffer++) = buf_get_u32((uint8_t*)&field1[i], 0, 32); free(field1); @@ -422,13 +427,13 @@ int xscale_read_tx(target_t *target, int consume) struct timeval timeout, now; scan_field_t fields[3]; - u8 field0_in = 0x0; - u8 field0_check_value = 0x2; - u8 field0_check_mask = 0x6; - u8 field2_check_value = 0x0; - u8 field2_check_mask = 0x1; + uint8_t field0_in = 0x0; + uint8_t field0_check_value = 0x2; + uint8_t field0_check_mask = 0x6; + uint8_t field2_check_value = 0x0; + uint8_t field2_check_mask = 0x1; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx); @@ -457,7 +462,7 @@ int xscale_read_tx(target_t *target, int consume) fields[2].tap = xscale->jtag_info.tap; fields[2].num_bits = 1; fields[2].out_value = NULL; - u8 tmp; + uint8_t tmp; fields[2].in_value = &tmp; gettimeofday(&timeout, NULL); @@ -476,10 +481,10 @@ int xscale_read_tx(target_t *target, int consume) jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path); } - jtag_add_dr_scan(3, fields, TAP_IDLE); + jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE)); - jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask); - jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask); + jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask); + jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -497,7 +502,7 @@ int xscale_read_tx(target_t *target, int consume) { goto done; } - if (debug_level>=3) + if (debug_level >= 3) { LOG_DEBUG("waiting 100ms"); alive_sleep(100); /* avoid flooding the logs */ @@ -523,15 +528,15 @@ int xscale_write_rx(target_t *target) struct timeval timeout, now; scan_field_t fields[3]; - u8 field0_out = 0x0; - u8 field0_in = 0x0; - u8 field0_check_value = 0x2; - u8 field0_check_mask = 0x6; - u8 field2 = 0x0; - u8 field2_check_value = 0x0; - u8 field2_check_mask = 0x1; + uint8_t field0_out = 0x0; + uint8_t field0_in = 0x0; + uint8_t field0_check_value = 0x2; + uint8_t field0_check_mask = 0x6; + uint8_t field2 = 0x0; + uint8_t field2_check_value = 0x0; + uint8_t field2_check_mask = 0x1; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx); @@ -549,7 +554,7 @@ int xscale_write_rx(target_t *target) fields[2].tap = xscale->jtag_info.tap; fields[2].num_bits = 1; fields[2].out_value = &field2; - u8 tmp; + uint8_t tmp; fields[2].in_value = &tmp; gettimeofday(&timeout, NULL); @@ -559,10 +564,10 @@ int xscale_write_rx(target_t *target) LOG_DEBUG("polling RX"); for (;;) { - jtag_add_dr_scan(3, fields, TAP_IDLE); + jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE)); - jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask); - jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask); + jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask); + jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -578,7 +583,7 @@ int xscale_write_rx(target_t *target) } if (!(field0_in & 1)) goto done; - if (debug_level>=3) + if (debug_level >= 3) { LOG_DEBUG("waiting 100ms"); alive_sleep(100); /* avoid flooding the logs */ @@ -591,7 +596,7 @@ int xscale_write_rx(target_t *target) /* set rx_valid */ field2 = 0x1; - jtag_add_dr_scan(3, fields, TAP_IDLE); + jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE)); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -603,18 +608,18 @@ int xscale_write_rx(target_t *target) } /* send count elements of size byte to the debug handler */ -int xscale_send(target_t *target, u8 *buffer, int count, int size) +int xscale_send(target_t *target, uint8_t *buffer, int count, int size) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - u32 t[3]; + uint32_t t[3]; int bits[3]; int retval; int done_count = 0; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx); @@ -657,7 +662,7 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size) 3, bits, t, - TAP_IDLE); + jtag_set_end_state(TAP_IDLE)); buffer += size; } @@ -670,7 +675,7 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size) return ERROR_OK; } -int xscale_send_u32(target_t *target, u32 value) +int xscale_send_u32(target_t *target, uint32_t value) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -687,12 +692,12 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) int retval; scan_field_t fields[3]; - u8 field0 = 0x0; - u8 field0_check_value = 0x2; - u8 field0_check_mask = 0x7; - u8 field2 = 0x0; - u8 field2_check_value = 0x0; - u8 field2_check_mask = 0x1; + uint8_t field0 = 0x0; + uint8_t field0_check_value = 0x2; + uint8_t field0_check_mask = 0x7; + uint8_t field2 = 0x0; + uint8_t field2_check_value = 0x0; + uint8_t field2_check_mask = 0x1; if (hold_rst != -1) xscale->hold_rst = hold_rst; @@ -700,7 +705,7 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) if (ext_dbg_brk != -1) xscale->external_debug_break = ext_dbg_brk; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); buf_set_u32(&field0, 1, 1, xscale->hold_rst); @@ -709,7 +714,7 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) fields[0].tap = xscale->jtag_info.tap; fields[0].num_bits = 3; fields[0].out_value = &field0; - u8 tmp; + uint8_t tmp; fields[0].in_value = &tmp; fields[1].tap = xscale->jtag_info.tap; @@ -721,13 +726,13 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) fields[2].tap = xscale->jtag_info.tap; fields[2].num_bits = 1; fields[2].out_value = &field2; - u8 tmp2; + uint8_t tmp2; fields[2].in_value = &tmp2; - jtag_add_dr_scan(3, fields, TAP_INVALID); + jtag_add_dr_scan(3, fields, jtag_get_end_state()); - jtag_check_value_mask(fields+0, &field0_check_value, &field0_check_mask); - jtag_check_value_mask(fields+2, &field2_check_value, &field2_check_mask); + jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask); + jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -753,19 +758,19 @@ unsigned int parity (unsigned int v) return (0x6996 >> v) & 1; } -int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8]) +int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buffer[8]) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - u8 packet[4]; - u8 cmd; + uint8_t packet[4]; + uint8_t cmd; int word; scan_field_t fields[2]; - LOG_DEBUG("loading miniIC at 0x%8.8x", va); + LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va); - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */ /* CMD is b010 for Main IC and b011 for Mini IC */ @@ -799,7 +804,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8]) - jtag_add_dr_scan(2, fields, TAP_INVALID); + jtag_add_dr_scan(2, fields, jtag_get_end_state()); fields[0].num_bits = 32; fields[0].out_value = packet; @@ -811,11 +816,11 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8]) { buf_set_u32(packet, 0, 32, buffer[word]); - u32 value; - memcpy(&value, packet, sizeof(u32)); + uint32_t value; + memcpy(&value, packet, sizeof(uint32_t)); cmd = parity(value); - jtag_add_dr_scan(2, fields, TAP_INVALID); + jtag_add_dr_scan(2, fields, jtag_get_end_state()); } jtag_execute_queue(); @@ -823,16 +828,16 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8]) return ERROR_OK; } -int xscale_invalidate_ic_line(target_t *target, u32 va) +int xscale_invalidate_ic_line(target_t *target, uint32_t va) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - u8 packet[4]; - u8 cmd; + uint8_t packet[4]; + uint8_t cmd; scan_field_t fields[2]; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */ /* CMD for invalidate IC line b000, bits [6:4] b000 */ @@ -861,7 +866,7 @@ int xscale_invalidate_ic_line(target_t *target, u32 va) - jtag_add_dr_scan(2, fields, TAP_INVALID); + jtag_add_dr_scan(2, fields, jtag_get_end_state()); return ERROR_OK; } @@ -873,7 +878,7 @@ int xscale_update_vectors(target_t *target) int i; int retval; - u32 low_reset_branch, high_reset_branch; + uint32_t low_reset_branch, high_reset_branch; for (i = 1; i < 8; i++) { @@ -884,10 +889,10 @@ int xscale_update_vectors(target_t *target) } else { - retval=target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]); + retval = target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]); if (retval == ERROR_TARGET_TIMEOUT) return retval; - if (retval!=ERROR_OK) + if (retval != ERROR_OK) { /* Some of these reads will fail as part of normal execution */ xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0); @@ -903,10 +908,10 @@ int xscale_update_vectors(target_t *target) } else { - retval=target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]); + retval = target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]); if (retval == ERROR_TARGET_TIMEOUT) return retval; - if (retval!=ERROR_OK) + if (retval != ERROR_OK) { /* Some of these reads will fail as part of normal execution */ xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0); @@ -953,11 +958,11 @@ int xscale_arch_state(struct target_s *target) } LOG_USER("target halted in %s state due to %s, current mode: %s\n" - "cpsr: 0x%8.8x pc: 0x%8.8x\n" + "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" "MMU: %s, D-Cache: %s, I-Cache: %s" "%s", armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name , + Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name , armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), @@ -971,7 +976,7 @@ int xscale_arch_state(struct target_s *target) int xscale_poll(target_t *target) { - int retval=ERROR_OK; + int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; @@ -1017,33 +1022,33 @@ int xscale_debug_entry(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - u32 pc; - u32 buffer[10]; + uint32_t pc; + uint32_t buffer[10]; int i; int retval; - u32 moe; + uint32_t moe; /* clear external dbg break (will be written on next DCSR read) */ xscale->external_debug_break = 0; - if ((retval=xscale_read_dcsr(target))!=ERROR_OK) + if ((retval = xscale_read_dcsr(target)) != ERROR_OK) return retval; /* get r0, pc, r1 to r7 and cpsr */ - if ((retval=xscale_receive(target, buffer, 10))!=ERROR_OK) + if ((retval = xscale_receive(target, buffer, 10)) != ERROR_OK) return retval; /* move r0 from buffer to register cache */ buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - LOG_DEBUG("r0: 0x%8.8x", buffer[0]); + LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]); /* move pc from buffer to register cache */ buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, buffer[1]); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - LOG_DEBUG("pc: 0x%8.8x", buffer[1]); + LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]); /* move data from buffer to register cache */ for (i = 1; i <= 7; i++) @@ -1051,13 +1056,13 @@ int xscale_debug_entry(target_t *target) buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]); armv4_5->core_cache->reg_list[i].dirty = 1; armv4_5->core_cache->reg_list[i].valid = 1; - LOG_DEBUG("r%i: 0x%8.8x", i, buffer[i + 1]); + LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]); } buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]); armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; - LOG_DEBUG("cpsr: 0x%8.8x", buffer[9]); + LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]); armv4_5->core_mode = buffer[9] & 0x1f; if (armv4_5_mode_to_number(armv4_5->core_mode) == -1) @@ -1156,7 +1161,7 @@ int xscale_debug_entry(target_t *target) /* on the first debug entry, identify cache type */ if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1) { - u32 cache_type_reg; + uint32_t cache_type_reg; /* read cp15 cache type register */ xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CACHETYPE]); @@ -1200,7 +1205,7 @@ int xscale_halt(target_t *target) xscale_common_t *xscale = armv4_5->arch_info; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); + target_state_name(target)); if (target->state == TARGET_HALTED) { @@ -1229,7 +1234,7 @@ int xscale_halt(target_t *target) return ERROR_OK; } -int xscale_enable_single_step(struct target_s *target, u32 next_pc) +int xscale_enable_single_step(struct target_s *target, uint32_t next_pc) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale= armv4_5->arch_info; @@ -1251,7 +1256,7 @@ int xscale_enable_single_step(struct target_s *target, u32 next_pc) } } - if ((retval=xscale_set_reg_u32(ibcr0, next_pc | 0x1))!=ERROR_OK) + if ((retval = xscale_set_reg_u32(ibcr0, next_pc | 0x1)) != ERROR_OK) return retval; return ERROR_OK; @@ -1264,19 +1269,19 @@ int xscale_disable_single_step(struct target_s *target) reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0]; int retval; - if ((retval=xscale_set_reg_u32(ibcr0, 0x0))!=ERROR_OK) + if ((retval = xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK) return retval; return ERROR_OK; } -int xscale_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution) +int xscale_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale= armv4_5->arch_info; breakpoint_t *breakpoint = target->breakpoints; - u32 current_pc; + uint32_t current_pc; int retval; int i; @@ -1295,7 +1300,7 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ } /* update vector tables */ - if ((retval=xscale_update_vectors(target))!=ERROR_OK) + if ((retval = xscale_update_vectors(target)) != ERROR_OK) return retval; /* current = 1: continue on current pc, otherwise continue at
*/ @@ -1316,18 +1321,18 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ { if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))) { - u32 next_pc; + uint32_t next_pc; /* there's a breakpoint at the current PC, we have to step over it */ - LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address); + LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address); xscale_unset_breakpoint(target, breakpoint); /* calculate PC of next instruction */ if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK) { - u32 current_opcode; + uint32_t current_opcode; target_read_u32(target, current_pc, ¤t_opcode); - LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); + LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode); } LOG_DEBUG("enable single-step"); @@ -1348,18 +1353,18 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ /* send CPSR */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); - LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); for (i = 7; i >= 0; i--) { /* send register */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); - LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); + LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); - LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); /* wait for and process debug entry */ xscale_debug_entry(target); @@ -1367,7 +1372,7 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ LOG_DEBUG("disable single-step"); xscale_disable_single_step(target); - LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address); + LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address); xscale_set_breakpoint(target, breakpoint); } } @@ -1391,18 +1396,18 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ /* send CPSR */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); - LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); for (i = 7; i >= 0; i--) { /* send register */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); - LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); + LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); - LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); target->debug_reason = DBG_REASON_NOTHALTED; @@ -1426,12 +1431,12 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_ return ERROR_OK; } -static int xscale_step_inner(struct target_s *target, int current, u32 address, int handle_breakpoints) +static int xscale_step_inner(struct target_s *target, int current, uint32_t address, int handle_breakpoints) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - u32 next_pc; + uint32_t next_pc; int retval; int i; @@ -1440,65 +1445,65 @@ static int xscale_step_inner(struct target_s *target, int current, u32 address, /* calculate PC of next instruction */ if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK) { - u32 current_opcode, current_pc; + uint32_t current_opcode, current_pc; current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); target_read_u32(target, current_pc, ¤t_opcode); - LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); + LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode); return retval; } LOG_DEBUG("enable single-step"); - if ((retval=xscale_enable_single_step(target, next_pc))!=ERROR_OK) + if ((retval = xscale_enable_single_step(target, next_pc)) != ERROR_OK) return retval; /* restore banked registers */ - if ((retval=xscale_restore_context(target))!=ERROR_OK) + if ((retval = xscale_restore_context(target)) != ERROR_OK) return retval; /* send resume request (command 0x30 or 0x31) * clean the trace buffer if it is to be enabled (0x62) */ if (xscale->trace.buffer_enabled) { - if ((retval=xscale_send_u32(target, 0x62))!=ERROR_OK) + if ((retval = xscale_send_u32(target, 0x62)) != ERROR_OK) return retval; - if ((retval=xscale_send_u32(target, 0x31))!=ERROR_OK) + if ((retval = xscale_send_u32(target, 0x31)) != ERROR_OK) return retval; } else - if ((retval=xscale_send_u32(target, 0x30))!=ERROR_OK) + if ((retval = xscale_send_u32(target, 0x30)) != ERROR_OK) return retval; /* send CPSR */ - if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)))!=ERROR_OK) + if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK) return retval; - LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); for (i = 7; i >= 0; i--) { /* send register */ - if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)))!=ERROR_OK) + if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32))) != ERROR_OK) return retval; - LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); + LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ - if ((retval=xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))!=ERROR_OK) + if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))) != ERROR_OK) return retval; - LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); target_call_event_callbacks(target, TARGET_EVENT_RESUMED); /* registers are now invalid */ - if ((retval=armv4_5_invalidate_core_regs(target))!=ERROR_OK) + if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK) return retval; /* wait for and process debug entry */ - if ((retval=xscale_debug_entry(target))!=ERROR_OK) + if ((retval = xscale_debug_entry(target)) != ERROR_OK) return retval; LOG_DEBUG("disable single-step"); - if ((retval=xscale_disable_single_step(target))!=ERROR_OK) + if ((retval = xscale_disable_single_step(target)) != ERROR_OK) return retval; target_call_event_callbacks(target, TARGET_EVENT_HALTED); @@ -1506,12 +1511,12 @@ static int xscale_step_inner(struct target_s *target, int current, u32 address, return ERROR_OK; } -int xscale_step(struct target_s *target, int current, u32 address, int handle_breakpoints) +int xscale_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) { armv4_5_common_t *armv4_5 = target->arch_info; breakpoint_t *breakpoint = target->breakpoints; - u32 current_pc; + uint32_t current_pc; int retval; if (target->state != TARGET_HALTED) @@ -1529,7 +1534,7 @@ int xscale_step(struct target_s *target, int current, u32 address, int handle_br /* if we're at the reset vector, we have to simulate the step */ if (current_pc == 0x0) { - if ((retval=arm_simulate_step(target, NULL))!=ERROR_OK) + if ((retval = arm_simulate_step(target, NULL)) != ERROR_OK) return retval; current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); @@ -1543,7 +1548,7 @@ int xscale_step(struct target_s *target, int current, u32 address, int handle_br if (handle_breakpoints) if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))) { - if ((retval=xscale_unset_breakpoint(target, breakpoint))!=ERROR_OK) + if ((retval = xscale_unset_breakpoint(target, breakpoint)) != ERROR_OK) return retval; } @@ -1566,12 +1571,12 @@ int xscale_assert_reset(target_t *target) xscale_common_t *xscale = armv4_5->arch_info; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); + target_state_name(target)); /* select DCSR instruction (set endstate to R-T-I to ensure we don't * end up in T-L-R, which would reset JTAG */ - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); /* set Hold reset, Halt mode and Trap Reset */ @@ -1595,7 +1600,7 @@ int xscale_assert_reset(target_t *target) if (target->reset_halt) { int retval; - if ((retval = target_halt(target))!=ERROR_OK) + if ((retval = target_halt(target)) != ERROR_OK) return retval; } @@ -1608,11 +1613,11 @@ int xscale_deassert_reset(target_t *target) xscale_common_t *xscale = armv4_5->arch_info; fileio_t debug_handler; - u32 address; - u32 binary_size; + uint32_t address; + uint32_t binary_size; - u32 buf_cnt; - u32 i; + uint32_t buf_cnt; + uint32_t i; int retval; breakpoint_t *breakpoint = target->breakpoints; @@ -1645,7 +1650,7 @@ int xscale_deassert_reset(target_t *target) /* wait 300ms; 150 and 100ms were not enough */ jtag_add_sleep(300*1000); - jtag_add_runtest(2030, TAP_IDLE); + jtag_add_runtest(2030, jtag_set_end_state(TAP_IDLE)); jtag_execute_queue(); /* set Hold reset, Halt mode and Trap Reset */ @@ -1676,8 +1681,8 @@ int xscale_deassert_reset(target_t *target) address = xscale->handler_address; while (binary_size > 0) { - u32 cache_line[8]; - u8 buffer[32]; + uint32_t cache_line[8]; + uint8_t buffer[32]; if ((retval = fileio_read(&debug_handler, 32, buffer, &buf_cnt)) != ERROR_OK) { @@ -1686,7 +1691,7 @@ int xscale_deassert_reset(target_t *target) for (i = 0; i < buf_cnt; i += 4) { - /* convert LE buffer to host-endian u32 */ + /* convert LE buffer to host-endian uint32_t */ cache_line[i / 4] = le_to_h_u32(&buffer[i]); } @@ -1708,7 +1713,7 @@ int xscale_deassert_reset(target_t *target) xscale_load_ic(target, 1, 0x0, xscale->low_vectors); xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors); - jtag_add_runtest(30, TAP_IDLE); + jtag_add_runtest(30, jtag_set_end_state(TAP_IDLE)); jtag_add_sleep(100000); @@ -1753,7 +1758,7 @@ int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod return ERROR_OK; } -int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value) +int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value) { return ERROR_OK; @@ -1763,7 +1768,7 @@ int xscale_full_context(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; - u32 *buffer; + uint32_t *buffer; int i, j; @@ -1781,7 +1786,7 @@ int xscale_full_context(target_t *target) * we can't enter User mode on an XScale (unpredictable), * but User shares registers with SYS */ - for(i = 1; i < 7; i++) + for (i = 1; i < 7; i++) { int valid = 1; @@ -1795,7 +1800,7 @@ int xscale_full_context(target_t *target) if (!valid) { - u32 tmp_cpsr; + uint32_t tmp_cpsr; /* request banked registers */ xscale_send_u32(target, 0x0); @@ -1853,7 +1858,7 @@ int xscale_restore_context(target_t *target) * we can't enter User mode on an XScale (unpredictable), * but User shares registers with SYS */ - for(i = 1; i < 7; i++) + for (i = 1; i < 7; i++) { int dirty = 0; @@ -1874,7 +1879,7 @@ int xscale_restore_context(target_t *target) if (dirty) { - u32 tmp_cpsr; + uint32_t tmp_cpsr; /* send banked registers */ xscale_send_u32(target, 0x1); @@ -1904,15 +1909,15 @@ int xscale_restore_context(target_t *target) return ERROR_OK; } -int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - u32 *buf32; - u32 i; + uint32_t *buf32; + uint32_t i; int retval; - LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); + LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32, address, size, count); if (target->state != TARGET_HALTED) { @@ -1928,20 +1933,20 @@ int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count return ERROR_TARGET_UNALIGNED_ACCESS; /* send memory read request (command 0x1n, n: access size) */ - if ((retval=xscale_send_u32(target, 0x10 | size))!=ERROR_OK) + if ((retval = xscale_send_u32(target, 0x10 | size)) != ERROR_OK) return retval; /* send base address for read request */ - if ((retval=xscale_send_u32(target, address))!=ERROR_OK) + if ((retval = xscale_send_u32(target, address)) != ERROR_OK) return retval; /* send number of requested data words */ - if ((retval=xscale_send_u32(target, count))!=ERROR_OK) + if ((retval = xscale_send_u32(target, count)) != ERROR_OK) return retval; /* receive data from target (count times 32-bit words in host endianness) */ buf32 = malloc(4 * count); - if ((retval=xscale_receive(target, buf32, count))!=ERROR_OK) + if ((retval = xscale_receive(target, buf32, count)) != ERROR_OK) return retval; /* extract data from host-endian buffer into byte stream */ @@ -1969,12 +1974,12 @@ int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count free(buf32); /* examine DCSR, to see if Sticky Abort (SA) got set */ - if ((retval=xscale_read_dcsr(target))!=ERROR_OK) + if ((retval = xscale_read_dcsr(target)) != ERROR_OK) return retval; if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) { /* clear SA bit */ - if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK) + if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK) return retval; return ERROR_TARGET_DATA_ABORT; @@ -1983,13 +1988,13 @@ int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count return ERROR_OK; } -int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; int retval; - LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); + LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32, address, size, count); if (target->state != TARGET_HALTED) { @@ -2005,15 +2010,15 @@ int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 coun return ERROR_TARGET_UNALIGNED_ACCESS; /* send memory write request (command 0x2n, n: access size) */ - if ((retval=xscale_send_u32(target, 0x20 | size))!=ERROR_OK) + if ((retval = xscale_send_u32(target, 0x20 | size)) != ERROR_OK) return retval; /* send base address for read request */ - if ((retval=xscale_send_u32(target, address))!=ERROR_OK) + if ((retval = xscale_send_u32(target, address)) != ERROR_OK) return retval; /* send number of requested data words to be written*/ - if ((retval=xscale_send_u32(target, count))!=ERROR_OK) + if ((retval = xscale_send_u32(target, count)) != ERROR_OK) return retval; /* extract data from host-endian buffer into byte stream */ @@ -2043,16 +2048,16 @@ int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 coun } } #endif - if ((retval=xscale_send(target, buffer, count, size))!=ERROR_OK) + if ((retval = xscale_send(target, buffer, count, size)) != ERROR_OK) return retval; /* examine DCSR, to see if Sticky Abort (SA) got set */ - if ((retval=xscale_read_dcsr(target))!=ERROR_OK) + if ((retval = xscale_read_dcsr(target)) != ERROR_OK) return retval; if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) { /* clear SA bit */ - if ((retval=xscale_send_u32(target, 0x60))!=ERROR_OK) + if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK) return retval; return ERROR_TARGET_DATA_ABORT; @@ -2061,16 +2066,16 @@ int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 coun return ERROR_OK; } -int xscale_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer) +int xscale_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer) { return xscale_write_memory(target, address, 4, count, buffer); } -u32 xscale_get_ttb(target_t *target) +uint32_t xscale_get_ttb(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - u32 ttb; + uint32_t ttb; xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]); ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32); @@ -2082,7 +2087,7 @@ void xscale_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_c { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - u32 cp15_control; + uint32_t cp15_control; /* read cp15 control register */ xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]); @@ -2121,7 +2126,7 @@ void xscale_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ca { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - u32 cp15_control; + uint32_t cp15_control; /* read cp15 control register */ xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]); @@ -2163,7 +2168,7 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (breakpoint->type == BKPT_HARD) { - u32 value = breakpoint->address | 1; + uint32_t value = breakpoint->address | 1; if (!xscale->ibcr0_used) { xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], value); @@ -2187,12 +2192,12 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (breakpoint->length == 4) { /* keep the original instruction in target endianness */ - if((retval = target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) + if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; } /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */ - if((retval = target_write_u32(target, breakpoint->address, xscale->arm_bkpt)) != ERROR_OK) + if ((retval = target_write_u32(target, breakpoint->address, xscale->arm_bkpt)) != ERROR_OK) { return retval; } @@ -2200,12 +2205,12 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) else { /* keep the original instruction in target endianness */ - if((retval = target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) + if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; } /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */ - if((retval = target_write_u32(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK) + if ((retval = target_write_u32(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK) { return retval; } @@ -2284,14 +2289,14 @@ int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) /* restore original instruction (kept in target endianness) */ if (breakpoint->length == 4) { - if((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) + if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; } } else { - if((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) + if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; } @@ -2328,9 +2333,9 @@ int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - u8 enable=0; + uint8_t enable = 0; reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON]; - u32 dbcon_value = buf_get_u32(dbcon->value, 0, 32); + uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32); if (target->state != TARGET_HALTED) { @@ -2411,7 +2416,7 @@ int xscale_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON]; - u32 dbcon_value = buf_get_u32(dbcon->value, 0, 32); + uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32); if (target->state != TARGET_HALTED) { @@ -2534,13 +2539,13 @@ int xscale_get_reg(reg_t *reg) return ERROR_OK; } -int xscale_set_reg(reg_t *reg, u8* buf) +int xscale_set_reg(reg_t *reg, uint8_t* buf) { xscale_reg_t *arch_info = reg->arch_info; target_t *target = arch_info->target; armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; - u32 value = buf_get_u32(buf, 0, 32); + uint32_t value = buf_get_u32(buf, 0, 32); /* DCSR, TX and RX are accessible via JTAG */ if (strcmp(reg->name, "XSCALE_DCSR") == 0) @@ -2580,16 +2585,16 @@ int xscale_set_reg(reg_t *reg, u8* buf) } /* convenience wrapper to access XScale specific registers */ -int xscale_set_reg_u32(reg_t *reg, u32 value) +int xscale_set_reg_u32(reg_t *reg, uint32_t value) { - u8 buf[4]; + uint8_t buf[4]; buf_set_u32(buf, 0, 32, value); return xscale_set_reg(reg, buf); } -int xscale_write_dcsr_sw(target_t *target, u32 value) +int xscale_write_dcsr_sw(target_t *target, uint32_t value) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -2621,7 +2626,7 @@ int xscale_read_trace(target_t *target) * 256 trace buffer entries * 2 checkpoint addresses */ - u32 trace_buffer[258]; + uint32_t trace_buffer[258]; int is_address[256]; int i, j; @@ -2696,8 +2701,8 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction) xscale_common_t *xscale = armv4_5->arch_info; int i; int section = -1; - u32 size_read; - u32 opcode; + uint32_t size_read; + uint32_t opcode; int retval; if (!xscale->trace.image) @@ -2722,7 +2727,7 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction) if (xscale->trace.core_state == ARMV4_5_STATE_ARM) { - u8 buf[4]; + uint8_t buf[4]; if ((retval = image_read_section(xscale->trace.image, section, xscale->trace.current_pc - xscale->trace.image->sections[section].base_address, 4, buf, &size_read)) != ERROR_OK) @@ -2735,7 +2740,7 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction) } else if (xscale->trace.core_state == ARMV4_5_STATE_THUMB) { - u8 buf[2]; + uint8_t buf[2]; if ((retval = image_read_section(xscale->trace.image, section, xscale->trace.current_pc - xscale->trace.image->sections[section].base_address, 2, buf, &size_read)) != ERROR_OK) @@ -2755,7 +2760,7 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction) return ERROR_OK; } -int xscale_branch_address(xscale_trace_data_t *trace_data, int i, u32 *target) +int xscale_branch_address(xscale_trace_data_t *trace_data, int i, uint32_t *target) { /* if there are less than four entries prior to the indirect branch message * we can't extract the address */ @@ -2776,7 +2781,7 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx) armv4_5_common_t *armv4_5 = target->arch_info; xscale_common_t *xscale = armv4_5->arch_info; int next_pc_ok = 0; - u32 next_pc = 0x0; + uint32_t next_pc = 0x0; xscale_trace_data_t *trace_data = xscale->trace.data; int retval; @@ -3017,7 +3022,7 @@ int xscale_quit(void) int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, jtag_tap_t *tap, const char *variant) { armv4_5_common_t *armv4_5; - u32 high_reset_branch, low_reset_branch; + uint32_t high_reset_branch, low_reset_branch; int i; armv4_5 = &xscale->armv4_5_common; @@ -3139,7 +3144,7 @@ int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char armv4_5_common_t *armv4_5; xscale_common_t *xscale; - u32 handler_address; + uint32_t handler_address; if (argc < 2) { @@ -3180,7 +3185,7 @@ int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, armv4_5_common_t *armv4_5; xscale_common_t *xscale; - u32 cache_clean_address; + uint32_t cache_clean_address; if (argc < 2) { @@ -3227,21 +3232,21 @@ int xscale_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cm return armv4_5_handle_cache_info_command(cmd_ctx, &xscale->armv4_5_mmu.armv4_5_cache); } -static int xscale_virt2phys(struct target_s *target, u32 virtual, u32 *physical) +static int xscale_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical) { armv4_5_common_t *armv4_5; xscale_common_t *xscale; int retval; int type; - u32 cb; + uint32_t cb; int domain; - u32 ap; + uint32_t ap; if ((retval = xscale_get_arch_pointers(target, &armv4_5, &xscale)) != ERROR_OK) { return retval; } - u32 ret = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu, virtual, &type, &cb, &domain, &ap); + uint32_t ret = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu, virtual, &type, &cb, &domain, &ap); if (type == -1) { return ret; @@ -3382,12 +3387,71 @@ int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, ch } +int xscale_handle_vector_table_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +{ + target_t *target = get_current_target(cmd_ctx); + armv4_5_common_t *armv4_5; + xscale_common_t *xscale; + int err = 0; + + if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK) + { + return ERROR_OK; + } + + if (argc == 0) /* print current settings */ + { + int idx; + + command_print(cmd_ctx, "active user-set static vectors:"); + for (idx = 1; idx < 8; idx++) + if (xscale->static_low_vectors_set & (1 << idx)) + command_print(cmd_ctx, "low %d: 0x%" PRIx32, idx, xscale->static_low_vectors[idx]); + for (idx = 1; idx < 8; idx++) + if (xscale->static_high_vectors_set & (1 << idx)) + command_print(cmd_ctx, "high %d: 0x%" PRIx32, idx, xscale->static_high_vectors[idx]); + return ERROR_OK; + } + + if (argc != 3) + err = 1; + else + { + int idx; + uint32_t vec; + idx = strtoul(args[1], NULL, 0); + vec = strtoul(args[2], NULL, 0); + + if (idx < 1 || idx >= 8) + err = 1; + + if (!err && strcmp(args[0], "low") == 0) + { + xscale->static_low_vectors_set |= (1<");
+
+ return ERROR_OK;
+}
+
+
int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
xscale_common_t *xscale;
- u32 dcsr_value;
+ uint32_t dcsr_value;
if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
{
@@ -3602,13 +3666,13 @@ int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int a
command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
return ERROR_OK;
}
- u32 reg_no = 0;
+ uint32_t reg_no = 0;
reg_t *reg = NULL;
- if(argc > 0)
+ if (argc > 0)
{
reg_no = strtoul(args[0], NULL, 0);
/*translate from xscale cp15 register no to openocd register*/
- switch(reg_no)
+ switch (reg_no)
{
case 0:
reg_no = XSCALE_MAINID;
@@ -3641,19 +3705,19 @@ int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int a
reg = &xscale->reg_cache->reg_list[reg_no];
}
- if(argc == 1)
+ if (argc == 1)
{
- u32 value;
+ uint32_t value;
/* read cp15 control register */
xscale_get_reg(reg);
value = buf_get_u32(reg->value, 0, 32);
- command_print(cmd_ctx, "%s (/%i): 0x%x", reg->name, reg->size, value);
+ command_print(cmd_ctx, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size), value);
}
- else if(argc == 2)
+ else if (argc == 2)
{
- u32 value = strtoul(args[1], NULL, 0);
+ uint32_t value = strtoul(args[1], NULL, 0);
/* send CP write request (command 0x41) */
xscale_send_u32(target, 0x41);
@@ -3690,8 +3754,9 @@ int xscale_register_commands(struct command_context_s *cmd_ctx)
register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache");
register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_vector_catch_command, COMMAND_EXEC, " of vectors that should be catched");
+ register_command(cmd_ctx, xscale_cmd, "vector_table", xscale_handle_vector_table_command, COMMAND_EXEC, " set static code for exception handler entry");
- register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, " ['fill' [n]|'wrap']");
+ register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, " ['fill' [n]|'wrap']");
register_command(cmd_ctx, xscale_cmd, "dump_trace", xscale_handle_dump_trace_command, COMMAND_EXEC, "dump content of trace buffer to ");
register_command(cmd_ctx, xscale_cmd, "analyze_trace", xscale_handle_analyze_trace_buffer_command, COMMAND_EXEC, "analyze content of trace buffer");