X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=FreeRTOS%2FDemo%2FCORTEX_A9_Zynq_ZC702%2FRTOSDemo_bsp%2Fps7_cortexa9_0%2Finclude%2Fxparameters.h;h=cfa88870ecc7ae4425d6fd77b01b22c28191e748;hb=2f3240cae4193f5662f4b8f24c4decdb2bc7778b;hp=06f11000051e82ac1193efca2065c5382cff7929;hpb=6e33f3d844560120d8110ec9d6a50f912b594b87;p=freertos diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xparameters.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xparameters.h index 06f110000..cfa88870e 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xparameters.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xparameters.h @@ -1,5 +1,8 @@ +#ifndef XPARAMETERS_H /* prevent circular inclusions */ +#define XPARAMETERS_H /* by using protection macros */ + /* Definition for CPU ID */ -#define XPAR_CPU_ID 0 +#define XPAR_CPU_ID 0U /* Definitions for peripheral PS7_CORTEXA9_0 */ #define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 @@ -20,6 +23,14 @@ /******************************************************************/ +/* Platform specific definitions */ +#define PLATFORM_ZYNQ + +/* Definitions for sleep timer configuration */ +#define XSLEEP_TIMER_IS_DEFAULT_TIMER + + +/******************************************************************/ /* Definitions for driver CANPS */ #define XPAR_XCANPS_NUM_INSTANCES 1 @@ -50,20 +61,20 @@ /******************************************************************/ /* Definitions for driver DEVCFG */ -#define XPAR_XDCFG_NUM_INSTANCES 1 +#define XPAR_XDCFG_NUM_INSTANCES 1U /* Definitions for peripheral PS7_DEV_CFG_0 */ -#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0 -#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000 -#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF +#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0U +#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000U +#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFU /******************************************************************/ /* Canonical definitions for peripheral PS7_DEV_CFG_0 */ #define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID -#define XPAR_XDCFG_0_BASEADDR 0xF8007000 -#define XPAR_XDCFG_0_HIGHADDR 0xF80070FF +#define XPAR_XDCFG_0_BASEADDR 0xF8007000U +#define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU /******************************************************************/ @@ -112,10 +123,12 @@ #define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50 +#define XPAR_PS7_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 0 /******************************************************************/ +#define XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT 0 /* Canonical definitions for peripheral PS7_ETHERNET_0 */ #define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID #define XPAR_XEMACPS_0_BASEADDR 0xE000B000 @@ -127,6 +140,7 @@ #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50 +#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 0 /******************************************************************/ @@ -275,6 +289,7 @@ #define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF #define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000 #define XPAR_PS7_QSPI_0_QSPI_MODE 0 +#define XPAR_PS7_QSPI_0_QSPI_BUS_WIDTH 2 /******************************************************************/ @@ -285,27 +300,28 @@ #define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF #define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000 #define XPAR_XQSPIPS_0_QSPI_MODE 0 +#define XPAR_XQSPIPS_0_QSPI_BUS_WIDTH 2 /******************************************************************/ /* Definitions for driver SCUGIC */ -#define XPAR_XSCUGIC_NUM_INSTANCES 1 +#define XPAR_XSCUGIC_NUM_INSTANCES 1U /* Definitions for peripheral PS7_SCUGIC_0 */ -#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0 -#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100 -#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF -#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000 +#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U +#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U +#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU +#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U /******************************************************************/ /* Canonical definitions for peripheral PS7_SCUGIC_0 */ -#define XPAR_SCUGIC_0_DEVICE_ID 0 -#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100 -#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF -#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000 +#define XPAR_SCUGIC_0_DEVICE_ID 0U +#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U +#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU +#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U /******************************************************************/ @@ -358,10 +374,14 @@ #define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000 #define XPAR_PS7_SD_0_HAS_CD 1 #define XPAR_PS7_SD_0_HAS_WP 1 +#define XPAR_PS7_SD_0_BUS_WIDTH 0 +#define XPAR_PS7_SD_0_MIO_BANK 0 +#define XPAR_PS7_SD_0_HAS_EMIO 0 /******************************************************************/ +#define XPAR_PS7_SD_0_IS_CACHE_COHERENT 0 /* Canonical definitions for peripheral PS7_SD_0 */ #define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID #define XPAR_XSDPS_0_BASEADDR 0xE0100000 @@ -369,45 +389,48 @@ #define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000 #define XPAR_XSDPS_0_HAS_CD 1 #define XPAR_XSDPS_0_HAS_WP 1 +#define XPAR_XSDPS_0_BUS_WIDTH 0 +#define XPAR_XSDPS_0_MIO_BANK 0 +#define XPAR_XSDPS_0_HAS_EMIO 0 /******************************************************************/ /* Definitions for driver TTCPS */ -#define XPAR_XTTCPS_NUM_INSTANCES 3 +#define XPAR_XTTCPS_NUM_INSTANCES 3U /* Definitions for peripheral PS7_TTC_0 */ -#define XPAR_PS7_TTC_0_DEVICE_ID 0 -#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000 -#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115 -#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0 -#define XPAR_PS7_TTC_1_DEVICE_ID 1 -#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004 -#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115 -#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0 -#define XPAR_PS7_TTC_2_DEVICE_ID 2 -#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008 -#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115 -#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0 +#define XPAR_PS7_TTC_0_DEVICE_ID 0U +#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000U +#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115U +#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0U +#define XPAR_PS7_TTC_1_DEVICE_ID 1U +#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004U +#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115U +#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0U +#define XPAR_PS7_TTC_2_DEVICE_ID 2U +#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008U +#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115U +#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0U /******************************************************************/ /* Canonical definitions for peripheral PS7_TTC_0 */ #define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID -#define XPAR_XTTCPS_0_BASEADDR 0xF8001000 -#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115 -#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_0_BASEADDR 0xF8001000U +#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115U +#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID -#define XPAR_XTTCPS_1_BASEADDR 0xF8001004 -#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115 -#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_1_BASEADDR 0xF8001004U +#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115U +#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID -#define XPAR_XTTCPS_2_BASEADDR 0xF8001008 -#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115 -#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_2_BASEADDR 0xF8001008U +#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115U +#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U /******************************************************************/ @@ -473,3 +496,4 @@ /******************************************************************/ +#endif /* end of protection macro */