X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=FreeRTOS%2FDemo%2FCORTEX_STM32L152_Discovery_IAR%2FSystem%2Fsystem_stm32l1xx.c;h=2ca0c4774221a068aee36090fc00689ee0504820;hb=10d2416d223cc4cdaa1cf894d8e33c6da645299a;hp=9676838934b595faaf1e61568aadb65b621de505;hpb=2da8f94490e882f9f10279f1daffcb15fd4c58eb;p=freertos diff --git a/FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/System/system_stm32l1xx.c b/FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/System/system_stm32l1xx.c index 967683893..2ca0c4774 100644 --- a/FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/System/system_stm32l1xx.c +++ b/FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/System/system_stm32l1xx.c @@ -8,69 +8,69 @@ * This file contains the system clock configuration for STM32L1xx Ultra * Low Medium-density devices, and is generated by the clock configuration * tool "STM32L1xx_Clock_Configuration_V1.0.0.xls". - * - * 1. This file provides two functions and one global variable to be called from + * + * 1. This file provides two functions and one global variable to be called from * user application: * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier * and Divider factors, AHB/APBx prescalers and Flash settings), - * depending on the configuration made in the clock xls tool. - * This function is called at startup just after reset and + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32l1xx_md.s" file. - * + * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick + * by the user application to setup the SysTick * timer or configure other parameters. - * + * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed - * during program execution. - * + * during program execution. + * * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source. * Then SystemInit() function is called, in "startup_stm32l1xx_md.s" file, to - * configure the system clock before to branch to main program. - * + * configure the system clock before to branch to main program. + * * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and MSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * + * function will do nothing and MSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define * in "stm32l1xx.h" file. When HSE is used as system clock source, directly or * through PLL, and you are using different crystal you have to adapt the HSE * value to your own configuration. - * - * 5. This file configures the system clock as follows: + * + * 5. This file configures the system clock as follows: *============================================================================= * System Clock Configuration *============================================================================= * System clock source | HSI - *----------------------------------------------------------------------------- + *----------------------------------------------------------------------------- * SYSCLK | 16000000 Hz - *----------------------------------------------------------------------------- + *----------------------------------------------------------------------------- * HCLK | 16000000 Hz - *----------------------------------------------------------------------------- + *----------------------------------------------------------------------------- * AHB Prescaler | 1 - *----------------------------------------------------------------------------- + *----------------------------------------------------------------------------- * APB1 Prescaler | 1 - *----------------------------------------------------------------------------- + *----------------------------------------------------------------------------- * APB2 Prescaler | 1 - *----------------------------------------------------------------------------- + *----------------------------------------------------------------------------- * HSE Frequency | 8000000 Hz - *----------------------------------------------------------------------------- + *----------------------------------------------------------------------------- * PLL DIV | Not Used - *----------------------------------------------------------------------------- + *----------------------------------------------------------------------------- * PLL MUL | Not Used - *----------------------------------------------------------------------------- + *----------------------------------------------------------------------------- * VDD | 3.3 V - *----------------------------------------------------------------------------- + *----------------------------------------------------------------------------- * Vcore | 1.8 V (Range 1) - *----------------------------------------------------------------------------- + *----------------------------------------------------------------------------- * Flash Latency | 0 WS - *----------------------------------------------------------------------------- + *----------------------------------------------------------------------------- * Require 48MHz for USB clock | Disabled - *----------------------------------------------------------------------------- + *----------------------------------------------------------------------------- *============================================================================= - ****************************************************************************** + ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS @@ -81,7 +81,7 @@ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** + ****************************************************************************** */ /** @addtogroup CMSIS @@ -90,8 +90,8 @@ /** @addtogroup stm32l1xx_system * @{ - */ - + */ + /** @addtogroup STM32L1xx_System_Private_Includes * @{ */ @@ -114,9 +114,9 @@ * @{ */ /*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ + Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ /** * @} @@ -145,7 +145,7 @@ __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9} * @{ */ -static void SetSysClock(void); +void SetSysClock(void); /** * @} @@ -157,7 +157,7 @@ static void SetSysClock(void); /** * @brief Setup the microcontroller system. - * Initialize the Embedded Flash Interface, the PLL and update the + * Initialize the Embedded Flash Interface, the PLL and update the * SystemCoreClock variable. * @param None * @retval None @@ -169,7 +169,7 @@ void SystemInit (void) /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ RCC->CFGR &= (uint32_t)0x88FFC00C; - + /*!< Reset HSION, HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xEEFEFFFE; @@ -181,7 +181,7 @@ void SystemInit (void) /*!< Disable all interrupts */ RCC->CIR = 0x00000000; - + /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ SetSysClock(); @@ -194,31 +194,31 @@ void SystemInit (void) /** * @brief Update SystemCoreClock according to Clock Register Values - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: - * - * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI * value as defined by the MSI range. - * + * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * + * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * + * * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * + * in voltage and temperature. + * * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value * 8 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. - * + * * - The result of this function could be not correct when using fractional - * value for HSE crystal. + * value for HSE crystal. * @param None * @retval None */ @@ -228,7 +228,7 @@ void SystemCoreClockUpdate (void) /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; - + switch (tmp) { case 0x00: /* MSI used as system clock */ @@ -247,7 +247,7 @@ void SystemCoreClockUpdate (void) plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; pllmul = PLLMulTable[(pllmul >> 18)]; plldiv = (plldiv >> 22) + 1; - + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; if (pllsource == 0x00) @@ -274,21 +274,21 @@ void SystemCoreClockUpdate (void) } /** - * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash + * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash * settings. - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). * @param None * @retval None */ -static void SetSysClock(void) +void SetSysClock(void) { __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ /* Enable HSI */ RCC->CR |= ((uint32_t)RCC_CR_HSION); - + /* Wait till HSI is ready and if Time out is reached exit */ do { @@ -303,39 +303,39 @@ static void SetSysClock(void) { HSIStatus = (uint32_t)0x00; } - + if (HSIStatus == (uint32_t)0x01) { /* Flash 0 wait state */ FLASH->ACR &= ~FLASH_ACR_LATENCY; - + /* Disable Prefetch Buffer */ FLASH->ACR &= ~FLASH_ACR_PRFTEN; /* Disable 64-bit access */ FLASH->ACR &= ~FLASH_ACR_ACC64; - + /* Power enable */ RCC->APB1ENR |= RCC_APB1ENR_PWREN; - + /* Select the Voltage Range 1 (1.8 V) */ PWR->CR = PWR_CR_VOS_0; - - + + /* Wait Until the Voltage Regulator is ready */ while((PWR->CSR & PWR_CSR_VOSF) != RESET) { } - + /* HCLK = SYSCLK /1*/ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; /* PCLK2 = HCLK /1*/ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - + /* PCLK1 = HCLK /1*/ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - + /* Select HSI as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI;