X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=FreeRTOS%2FSource%2Fportable%2FIAR%2FAtmelSAM7S64%2Fportasm.s79;h=1aaacd044a5f29dccb9ea264f982520b51292fcc;hb=3d511cabadf346c67f0f56e15e999c02ca0393ed;hp=3f3b65ce8d913b02037b01f434a3eb0a93b5181c;hpb=4fc98ea9360d27da61c0096a3a46abcf64ca400d;p=freertos diff --git a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portasm.s79 b/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portasm.s79 index 3f3b65ce8..1aaacd044 100644 --- a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portasm.s79 +++ b/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portasm.s79 @@ -1,5 +1,6 @@ ;/* -; FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd. +; FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd. +; All rights reserved ; ; ; *************************************************************************** @@ -54,7 +55,7 @@ CODE32 EXTERN vTaskSwitchContext - EXTERN vTaskIncrementTick + EXTERN xTaskIncrementTick PUBLIC vPortYieldProcessor PUBLIC vPortPreemptiveTick @@ -74,10 +75,10 @@ vPortStartFirstTask: ; Manual context switch function. This is the SWI hander. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; vPortYieldProcessor: - ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly - ; as if the context was saved during and IRQ + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ ; handler. - + portSAVE_CONTEXT ; Save the context of the current task... LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. mov lr, pc @@ -91,13 +92,16 @@ vPortYieldProcessor: vPortPreemptiveTick: portSAVE_CONTEXT ; Save the context of the current task. - LDR R0, =vTaskIncrementTick ; Increment the tick count - this may wake a task. + LDR R0, =xTaskIncrementTick ; Increment the tick count - this may wake a task. mov lr, pc BX R0 + + CMP R0, #0 + BEQ SkipContextSwitch LDR R0, =vTaskSwitchContext ; Select the next task to execute. mov lr, pc BX R0 - +SkipContextSwitch LDR R14, =AT91C_BASE_PITC ; Clear the PIT interrupt LDR R0, [R14, #PITC_PIVR ]