X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=FreeRTOS%2FSource%2Fportable%2FMPLAB%2FPIC32MX%2Fport_asm.S;h=f47b1b22f898277514fb2dc16dafed5f524d502d;hb=bd94a7fd5cb8d9225bbd3568941b8e2da7cabd5e;hp=39678efef1fe2cf2235647359af6744fd5725a48;hpb=b18af6b07e944b8c932a9be32fbce2344510896c;p=freertos diff --git a/FreeRTOS/Source/portable/MPLAB/PIC32MX/port_asm.S b/FreeRTOS/Source/portable/MPLAB/PIC32MX/port_asm.S index 39678efef..f47b1b22f 100644 --- a/FreeRTOS/Source/portable/MPLAB/PIC32MX/port_asm.S +++ b/FreeRTOS/Source/portable/MPLAB/PIC32MX/port_asm.S @@ -1,68 +1,31 @@ /* - FreeRTOS V7.5.0 - Copyright (C) 2013 Real Time Engineers Ltd. - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -#include + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#include #include #include "ISR_Support.h" @@ -101,7 +64,7 @@ vPortTickInterruptHandler: .set noreorder .set noat - .ent xPortStartScheduler + .ent vPortStartFirstTask vPortStartFirstTask: @@ -109,35 +72,32 @@ vPortStartFirstTask: created so far. */ portRESTORE_CONTEXT - .end xPortStartScheduler + .end vPortStartFirstTask /*******************************************************************/ - .set noreorder + .set noreorder .set noat - .ent vPortYieldISR + .ent vPortYieldISR vPortYieldISR: /* Make room for the context. First save the current status so it can be - manipulated, and the cause and EPC registers so thier original values are - captured. */ - mfc0 k0, _CP0_CAUSE - addiu sp, sp, -portCONTEXT_SIZE + manipulated. */ + addiu sp, sp, -portCONTEXT_SIZE mfc0 k1, _CP0_STATUS - /* Also save s6 and s5 so we can use them during this interrupt. Any - nesting interrupts should maintain the values of these registers - across the ISR. */ + /* Also save s6 and s5 so they can be used. Any nesting interrupts should + maintain the values of these registers across the ISR. */ sw s6, 44(sp) sw s5, 40(sp) sw k1, portSTATUS_STACK_LOCATION(sp) - /* Interrupts above the kernel priority are going to be re-enabled. */ - srl k0, k0, 0xa - ins k1, k0, 10, 6 + /* Prepare to re-enabled interrupt above the kernel priority. */ + ins k1, zero, 10, 6 + ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) ins k1, zero, 1, 4 /* s5 is used as the frame pointer. */ @@ -158,16 +118,16 @@ vPortYieldISR: after interrupts are enabled. */ mfc0 s6, _CP0_EPC - /* Re-enable interrupts. */ + /* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ mtc0 k1, _CP0_STATUS /* Save the context into the space just created. s6 is saved again here as it now contains the EPC value. */ - sw ra, 120(s5) + sw ra, 120(s5) sw s8, 116(s5) sw t9, 112(s5) - sw t8, 108(s5) - sw t7, 104(s5) + sw t8, 108(s5) + sw t7, 104(s5) sw t6, 100(s5) sw t5, 96(s5) sw t4, 92(s5) @@ -184,7 +144,7 @@ vPortYieldISR: sw s7, 48(s5) sw s6, portEPC_STACK_LOCATION(s5) /* s5 and s6 has already been saved. */ - sw s4, 36(s5) + sw s4, 36(s5) sw s3, 32(s5) sw s2, 28(s5) sw s1, 24(s5) @@ -208,18 +168,21 @@ vPortYieldISR: is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever raise the IPL value and never lower it. */ di + ehb mfc0 s7, _CP0_STATUS - ins s7, $0, 10, 6 + ins s7, zero, 10, 6 ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1 /* This mtc0 re-enables interrupts, but only above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ mtc0 s6, _CP0_STATUS + ehb /* Clear the software interrupt in the core. */ mfc0 s6, _CP0_CAUSE ins s6, zero, 8, 1 mtc0 s6, _CP0_CAUSE + ehb /* Clear the interrupt in the interrupt controller. */ la s6, IFS0CLR @@ -231,6 +194,7 @@ vPortYieldISR: /* Clear the interrupt mask again. The saved status value is still in s7. */ mtc0 s7, _CP0_STATUS + ehb /* Restore the stack pointer from the TCB. */ la s0, pxCurrentTCB @@ -272,6 +236,7 @@ vPortYieldISR: /* Protect access to the k registers, and others. */ di + ehb /* Set nesting back to zero. As the lowest priority interrupt this interrupt cannot have nested. */ @@ -289,10 +254,11 @@ vPortYieldISR: lw k0, portEPC_STACK_LOCATION(sp) /* Remove stack frame. */ - addiu sp, sp, portCONTEXT_SIZE + addiu sp, sp, portCONTEXT_SIZE mtc0 k1, _CP0_STATUS mtc0 k0, _CP0_EPC + ehb eret nop