X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=README;h=68d6a499c09f8166baa475f575bdd29ebebc59be;hb=bae5b97e8ec0fedb50350a14e76648714bc51c99;hp=5ffe14b777177efc67382c7da0bef8727b9976b5;hpb=b2482dffa04b79f3878117364c1f3cbf7771117f;p=u-boot diff --git a/README b/README index 5ffe14b777..68d6a499c0 100644 --- a/README +++ b/README @@ -695,11 +695,6 @@ The following options need to be configured: This causes ft_system_setup() to be called before booting the kernel. - CONFIG_OF_BOOT_CPU - - This define fills in the correct boot CPU in the boot - param header, the default value is zero if undefined. - CONFIG_OF_IDE_FIXUP U-Boot can detect if an IDE device is present or not. @@ -1302,10 +1297,6 @@ The following options need to be configured: CONFIG_LAN91C96 Support for SMSC's LAN91C96 chips. - CONFIG_LAN91C96_BASE - Define this to hold the physical address - of the LAN91C96's I/O space - CONFIG_LAN91C96_USE_32_BIT Define this to enable 32 bit addressing @@ -1370,7 +1361,7 @@ The following options need to be configured: - PWM Support: CONFIG_PWM_IMX - Support for PWM modul on the imx6. + Support for PWM module on the imx6. - TPM Support: CONFIG_TPM @@ -1490,10 +1481,6 @@ The following options need to be configured: Derive USB clock from external clock "blah" - CONFIG_SYS_USB_EXTC_CLK 0x02 - CONFIG_SYS_USB_BRG_CLK 0xBLAH - Derive USB clock from brgclk - - CONFIG_SYS_USB_BRG_CLK 0x04 - If you have a USB-IF assigned VendorID then you may wish to define your own vendor specific values either in BoardName.h or directly in usbd_vendor_info.h. If you don't define @@ -2293,8 +2280,6 @@ CBFS (Coreboot Filesystem) support - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3 - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4 - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4 - - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5 - - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5 - CONFIG_SYS_I2C_SH_NUM_CONTROLLERS for number of i2c buses - drivers/i2c/omap24xx_i2c.c @@ -2348,10 +2333,7 @@ CBFS (Coreboot Filesystem) support additional defines: CONFIG_SYS_NUM_I2C_BUSES - Hold the number of i2c buses you want to use. If you - don't use/have i2c muxes on your i2c bus, this - is equal to CONFIG_SYS_NUM_I2C_ADAPTERS, and you can - omit this define. + Hold the number of i2c buses you want to use. CONFIG_SYS_I2C_DIRECT_BUS define this, if you don't use i2c muxes on your hardware. @@ -2565,7 +2547,7 @@ CBFS (Coreboot Filesystem) support will skip addresses 0x50 and 0x68 on a board with one I2C bus #define CONFIG_I2C_MULTI_BUS - #define CONFIG_SYS_I2C_MULTI_NOPROBES {{0,0x50},{0,0x68},{1,0x54}} + #define CONFIG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}} will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1 @@ -4505,7 +4487,7 @@ Low Level (hardware related) configuration options: CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial data is located at the end of the available space (sometimes written as (CONFIG_SYS_INIT_RAM_SIZE - - CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just + GENERATED_GBL_DATA_SIZE), and the initial stack is just below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) downward. @@ -4564,11 +4546,6 @@ Low Level (hardware related) configuration options: enable SPI microcode relocation patch (MPC8xx); define relocation offset in DPRAM [SCC4] -- CONFIG_SYS_USE_OSCCLK: - Use OSCM clock mode on MBX8xx board. Be careful, - wrong setting might damage your board. Read - doc/README.MBX before setting this variable! - - CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only) Offset of the bootmode word in DPRAM used by post (Power On Self Tests). This definition overrides @@ -4812,10 +4789,6 @@ within that device. Specifies that QE/FMAN firmware is located on the primary SD/MMC device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device. -- CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH - Specifies that QE/FMAN firmware is located on the primary SPI - device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device. - - CONFIG_SYS_QE_FMAN_FW_IN_REMOTE Specifies that QE/FMAN firmware is located in the remote (master) memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which @@ -4834,22 +4807,6 @@ within that device. - CONFIG_FSL_MC_ENET Enable the MC driver for Layerscape SoCs. -- CONFIG_SYS_LS_MC_FW_ADDR - The address in the storage device where the firmware is located. The - meaning of this address depends on which CONFIG_SYS_LS_MC_FW_IN_xxx macro - is also specified. - -- CONFIG_SYS_LS_MC_FW_LENGTH - The maximum possible size of the firmware. The firmware binary format - has a field that specifies the actual size of the firmware, but it - might not be possible to read any part of the firmware unless some - local storage is allocated to hold the entire firmware first. - -- CONFIG_SYS_LS_MC_FW_IN_NOR - Specifies that MC firmware is located in NOR flash, mapped as - normal addressable memory via the LBC. CONFIG_SYS_LS_MC_FW_ADDR is the - virtual address in NOR flash. - Freescale Layerscape Debug Server Support: ------------------------------------------- The Freescale Layerscape Debug Server Support supports the loading of