X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=README;h=76b150005f8d1f63ea36fd92e02c06411fdb3eda;hb=e80ab3e661428149105b5454c6111d17ddfb3b40;hp=d7e5b76295d22b0b3a90ad3cdee1db0e82de9000;hpb=ba8e76bd49a0575a2442025507882b499856af2b;p=u-boot

diff --git a/README b/README
index d7e5b76295..76b150005f 100644
--- a/README
+++ b/README
@@ -356,6 +356,13 @@ The following options need to be configured:
 		Define this option if you want to enable the
 		ICache only when Code runs from RAM.
 
+- 85xx CPU Options:
+		CONFIG_SYS_FSL_TBCLK_DIV
+
+		Defines the core time base clock divider ratio compared to the
+		system clock.  On most PQ3 devices this is 8, on newer QorIQ
+		devices it can be 16 or 32.  The ratio varies from SoC to Soc.
+
 - Intel Monahans options:
 		CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 
@@ -2751,6 +2758,14 @@ Low Level (hardware related) configuration options:
 		source code. It is used to make hardware dependant
 		initializations.
 
+- CONFIG_IDE_AHB:
+		Most IDE controllers were designed to be connected with PCI
+		interface. Only few of them were designed for AHB interface.
+		When software is doing ATA command and data transfer to
+		IDE devices through IDE-AHB controller, some additional
+		registers accessing to these kind of IDE-AHB controller
+		is requierd.
+
 - CONFIG_SYS_IMMR:	Physical address of the Internal Memory.
 		DO NOT CHANGE unless you know exactly what you're
 		doing! (11-4) [MPC8xx/82xx systems only]