X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=README;h=cb96322fb71d0e4301182759fa53c4afdc6b3167;hb=6b50f62cc4df7e2961fb45980cf91bb424ee263b;hp=8f0b38cbf38b16de6f2a9d8707cde096f3b52b51;hpb=a891601ce51edbafa1a2750c96a618e4fcbca1c2;p=u-boot diff --git a/README b/README index 8f0b38cbf3..cb96322fb7 100644 --- a/README +++ b/README @@ -141,7 +141,6 @@ Directory Hierarchy: /s3c24x0 Files specific to Samsung S3C24X0 CPUs /arm926ejs Files specific to ARM 926 CPUs /arm1136 Files specific to ARM 1136 CPUs - /ixp Files specific to Intel XScale IXP CPUs /pxa Files specific to Intel XScale PXA CPUs /sa1100 Files specific to Intel StrongARM SA1100 CPUs /lib Architecture specific library files @@ -423,6 +422,15 @@ The following options need to be configured: CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT This value denotes start offset of DSP CCSR space. + CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + Single Source Clock is clocking mode present in some of FSL SoC's. + In this mode, a single differential clock is used to supply + clocks to the sysclock, ddrclock and usbclock. + + CONFIG_SYS_CPC_REINIT_F + This CONFIG is defined when the CPC is configured as SRAM at the + time of U-boot entry and is required to be re-initialized. + - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN @@ -467,6 +475,37 @@ The following options need to be configured: Board config to use DDR3. It can be enabled for SoCs with Freescale DDR3 controllers. + CONFIG_SYS_FSL_IFC_BE + Defines the IFC controller register space as Big Endian + + CONFIG_SYS_FSL_IFC_LE + Defines the IFC controller register space as Little Endian + + CONFIG_SYS_FSL_PBL_PBI + It enables addition of RCW (Power on reset configuration) in built image. + Please refer doc/README.pblimage for more details + + CONFIG_SYS_FSL_PBL_RCW + It adds PBI(pre-boot instructions) commands in u-boot build image. + PBI commands can be used to configure SoC before it starts the execution. + Please refer doc/README.pblimage for more details + + CONFIG_SYS_FSL_DDR_BE + Defines the DDR controller register space as Big Endian + + CONFIG_SYS_FSL_DDR_LE + Defines the DDR controller register space as Little Endian + + CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY + Physical address from the view of DDR controllers. It is the + same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But + it could be different for ARM SoCs. + + CONFIG_SYS_FSL_DDR_INTLV_256B + DDR controller interleaving on 256-byte. This is a special + interleaving mode, handled by Dickens for Freescale layerscape + SoCs with ARM core. + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO @@ -531,6 +570,8 @@ The following options need to be configured: CONFIG_ARM_ERRATA_742230 CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 + CONFIG_ARM_ERRATA_794072 + CONFIG_ARM_ERRATA_761320 If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the @@ -875,6 +916,7 @@ The following options need to be configured: The default command configuration includes all commands except those marked below with a "*". + CONFIG_CMD_AES AES 128 CBC encrypt/decrypt CONFIG_CMD_ASKENV * ask for env variable CONFIG_CMD_BDI bdinfo CONFIG_CMD_BEDBUG * Include BedBug Debugger @@ -882,6 +924,7 @@ The following options need to be configured: CONFIG_CMD_BSP * Board specific commands CONFIG_CMD_BOOTD bootd CONFIG_CMD_CACHE * icache, dcache + CONFIG_CMD_CLK * clock command support CONFIG_CMD_CONSOLE coninfo CONFIG_CMD_CRC32 * crc32 CONFIG_CMD_DATE * support for RTC, date/time... @@ -902,10 +945,11 @@ The following options need to be configured: CONFIG_CMD_EXPORTENV * export the environment CONFIG_CMD_EXT2 * ext2 command support CONFIG_CMD_EXT4 * ext4 command support + CONFIG_CMD_FS_GENERIC * filesystem commands (e.g. load, ls) + that work for multiple fs types CONFIG_CMD_SAVEENV saveenv CONFIG_CMD_FDC * Floppy Disk Support CONFIG_CMD_FAT * FAT command support - CONFIG_CMD_FDOS * Dos diskette Support CONFIG_CMD_FLASH flinfo, erase, protect CONFIG_CMD_FPGA FPGA device initialization support CONFIG_CMD_FUSE * Device fuse support @@ -975,7 +1019,7 @@ The following options need to be configured: CONFIG_CMD_CDP * Cisco Discover Protocol support CONFIG_CMD_MFSL * Microblaze FSL support CONFIG_CMD_XIMG Load part of Multi Image - + CONFIG_CMD_UUID * Generate random UUID or GUID string EXAMPLE: If you want all functions except of network support you can write: @@ -1488,6 +1532,16 @@ The following options need to be configured: this to the maximum filesize (in bytes) for the buffer. Default is 4 MiB if undefined. + DFU_DEFAULT_POLL_TIMEOUT + Poll timeout [ms], is the timeout a device can send to the + host. The host must wait for this timeout before sending + a subsequent DFU_GET_STATUS request to the device. + + DFU_MANIFEST_POLL_TIMEOUT + Poll timeout [ms], which the device sends to the host when + entering dfuMANIFEST state. Host waits this timeout, before + sending again an USB request to the device. + - Journaling Flash filesystem support: CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE, CONFIG_JFFS2_NAND_DEV @@ -1704,7 +1758,7 @@ CBFS (Coreboot Filesystem) support If this option is set, then U-Boot will prevent the environment variable "splashimage" from being set to a problematic address - (see README.displaying-bmps and README.arm-unaligned-accesses). + (see README.displaying-bmps). This option is useful for targets where, due to alignment restrictions, an improperly aligned BMP image will cause a data abort. If you think you will not have problems with unaligned @@ -2751,6 +2805,12 @@ CBFS (Coreboot Filesystem) support Define this option to use the Bank addr/Extended addr support on SPI flashes which has size > 16Mbytes. + CONFIG_SF_DUAL_FLASH Dual flash memories + + Define this option to use dual flash support where two flash + memories can be connected with a given cs line. + currently Xilinx Zynq qspi support these type of connections. + - SystemACE Support: CONFIG_SYSTEMACE @@ -2821,11 +2881,31 @@ CBFS (Coreboot Filesystem) support CONFIG_RSA This enables the RSA algorithm used for FIT image verification - in U-Boot. See doc/uImage/signature for more information. + in U-Boot. See doc/uImage.FIT/signature.txt for more information. The signing part is build into mkimage regardless of this option. +- bootcount support: + CONFIG_BOOTCOUNT_LIMIT + + This enables the bootcounter support, see: + http://www.denx.de/wiki/DULG/UBootBootCountLimit + + CONFIG_AT91SAM9XE + enable special bootcounter support on at91sam9xe based boards. + CONFIG_BLACKFIN + enable special bootcounter support on blackfin based boards. + CONFIG_SOC_DA8XX + enable special bootcounter support on da850 based boards. + CONFIG_BOOTCOUNT_RAM + enable support for the bootcounter in RAM + CONFIG_BOOTCOUNT_I2C + enable support for the bootcounter on an i2c (like RTC) device. + CONFIG_SYS_I2C_RTC_ADDR = i2c chip address + CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for + the bootcounter. + CONFIG_BOOTCOUNT_ALEN = address len - Show boot progress: CONFIG_SHOW_BOOT_PROGRESS @@ -3267,6 +3347,9 @@ FIT uImage format: Defines the size and behavior of the NAND that SPL uses to read U-Boot + CONFIG_SPL_NAND_BOOT + Add support NAND boot + CONFIG_SYS_NAND_U_BOOT_OFFS Location in NAND to read U-Boot from @@ -3404,6 +3487,9 @@ typically in board_init_f() and board_init_r(). Configuration Settings: ----------------------- +- CONFIG_SYS_SUPPORT_64BIT_DATA: Defined automatically if compiled as 64-bit. + Optionally it can be defined to support 64-bit memory commands. + - CONFIG_SYS_LONGHELP: Defined when you want long help messages included; undefine this when you're short of memory. @@ -3676,12 +3762,6 @@ Configuration Settings: its config.mk file). If you find problems enabling this option on your board please report the problem and send patches! -- CONFIG_SYS_SYM_OFFSETS - This is set by architectures that use offsets for link symbols - instead of absolute values. So bss_start is obtained using an - offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than - directly. You should not need to touch this setting. - - CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only) This is set by OMAP boards for the max time that reset should be asserted. See doc/README.omap-reset-time for details on how @@ -4422,8 +4502,13 @@ This firmware often needs to be loaded during U-Boot booting, so macros are used to identify the storage device (NOR flash, SPI, etc) and the address within that device. -- CONFIG_SYS_QE_FMAN_FW_ADDR - The address in the storage device where the firmware is located. The +- CONFIG_SYS_FMAN_FW_ADDR + The address in the storage device where the FMAN microcode is located. The + meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro + is also specified. + +- CONFIG_SYS_QE_FW_ADDR + The address in the storage device where the QE microcode is located. The meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro is also specified. @@ -5252,6 +5337,15 @@ when your kernel is intended to use an initial ramdisk: Load Address: 0x00000000 Entry Point: 0x00000000 +The "dumpimage" is a tool to disassemble images built by mkimage. Its "-i" +option performs the converse operation of the mkimage's second form (the "-d" +option). Given an image built by mkimage, the dumpimage extracts a "data file" +from the image: + + tools/dumpimage -i image -p position data_file + -i ==> extract from the 'image' a specific 'data_file', \ + indexed by 'position' + Installing a Linux Image: -------------------------