X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farm1136%2Fcpu.c;h=b98e3d9face97006d5588901eecb152b2d799701;hb=b809b3ac13e1016b2be937bd4511973f90982ad2;hp=f2e30b51985f2e2f1272d7115434f52f65abd509;hpb=219872c8fe890cd280cf54f27df86504bb17d277;p=u-boot

diff --git a/arch/arm/cpu/arm1136/cpu.c b/arch/arm/cpu/arm1136/cpu.c
index f2e30b5198..b98e3d9fac 100644
--- a/arch/arm/cpu/arm1136/cpu.c
+++ b/arch/arm/cpu/arm1136/cpu.c
@@ -70,10 +70,12 @@ int cleanup_before_linux (void)
 static void cache_flush(void)
 {
 	unsigned long i = 0;
-
-	asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i)); /* clean entire data cache */
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));  /* invalidate both caches and flush btb */
-	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
+	/* clean entire data cache */
+	asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
+	/* invalidate both caches and flush btb */
+	asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
+	/* mem barrier to sync things */
+	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
 }
 
 #ifndef CONFIG_SYS_DCACHE_OFF
@@ -84,16 +86,16 @@ static void cache_flush(void)
 
 void invalidate_dcache_all(void)
 {
-	asm ("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+	asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
 }
 
 void flush_dcache_all(void)
 {
-	asm ("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
-	asm ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+	asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
+	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
 }
 
-static inline int bad_cache_range(unsigned long start, unsigned long stop)
+static int check_cache_range(unsigned long start, unsigned long stop)
 {
 	int ok = 1;
 
@@ -112,26 +114,26 @@ static inline int bad_cache_range(unsigned long start, unsigned long stop)
 
 void invalidate_dcache_range(unsigned long start, unsigned long stop)
 {
-	if (bad_cache_range(start, stop))
+	if (!check_cache_range(start, stop))
 		return;
 
 	while (start < stop) {
-		asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
+		asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
 		start += CONFIG_SYS_CACHELINE_SIZE;
 	}
 }
 
 void flush_dcache_range(unsigned long start, unsigned long stop)
 {
-	if (bad_cache_range(start, stop))
+	if (!check_cache_range(start, stop))
 		return;
 
 	while (start < stop) {
-		asm ("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
+		asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
 		start += CONFIG_SYS_CACHELINE_SIZE;
 	}
 
-	asm ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+	asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
 }
 
 void flush_cache(unsigned long start, unsigned long size)