X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farm1176%2Fstart.S;h=7c00201dd0ab7689604797922141045ae3235838;hb=e920f607793a0846b3837924e8ea5e95f2adc29b;hp=ac937bf5b085066a79a024dce4efaaffd9e3683b;hpb=b9cb64825b5e6efeb715abd8b48d9b12f98973e9;p=u-boot diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index ac937bf5b0..7c00201dd0 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -16,7 +16,7 @@ #include #include -#include +#include #ifndef CONFIG_SYS_PHY_UBOOT_BASE #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE @@ -38,6 +38,11 @@ .globl reset reset: + /* Allow the board to save important registers */ + b save_boot_params +.globl save_boot_params_ret +save_boot_params_ret: + /* * set the cpu to SVC32 mode */ @@ -79,7 +84,7 @@ cpu_init_crit: mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00000002 @ set bit 1 (A) Align orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache /* Prepare to disable the MMU */ @@ -111,3 +116,7 @@ mmu_disable_phys: c_runtime_cpu_setup: mov pc, lr + +WEAK(save_boot_params) + b save_boot_params_ret /* back to my caller */ +ENDPROC(save_boot_params)