X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farm926ejs%2Fcache.c;h=e86c2edd3bbfa160d22eeb224990b40e4657ae65;hb=9f5f51540d0d6af03ff22f55b7afc3fda6a4120d;hp=5b23e3a71b759db16dc7e14deab73b4c72d80aa8;hpb=a4aaad704827616a94c76f0a8efe06555c363545;p=u-boot

diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 5b23e3a71b..e86c2edd3b 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -2,22 +2,7 @@
  * (C) Copyright 2011
  * Ilya Yanok, EmCraft Systems
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <linux/types.h>
 #include <common.h>
@@ -30,7 +15,7 @@
 
 void invalidate_dcache_all(void)
 {
-	asm volatile("mcr p15, 0, %0, c7, c6, 0\n"::"r"(0));
+	asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
 }
 
 void flush_dcache_all(void)
@@ -40,7 +25,7 @@ void flush_dcache_all(void)
 		"mrc p15, 0, r15, c7, c14, 3\n"
 		"bne 0b\n"
 		"mcr p15, 0, %0, c7, c10, 4\n"
-		::"r"(0):"memory"
+		 : : "r"(0) : "memory"
 	);
 }
 
@@ -55,7 +40,7 @@ static int check_cache_range(unsigned long start, unsigned long stop)
 		ok = 0;
 
 	if (!ok)
-		printf("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
 			start, stop);
 
 	return ok;
@@ -67,7 +52,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop)
 		return;
 
 	while (start < stop) {
-		asm volatile("mcr p15, 0, %0, c7, c6, 1\n"::"r"(start));
+		asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
 		start += CONFIG_SYS_CACHELINE_SIZE;
 	}
 }
@@ -78,11 +63,11 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 		return;
 
 	while (start < stop) {
-		asm volatile("mcr p15, 0, %0, c7, c14, 1\n"::"r"(start));
+		asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start));
 		start += CONFIG_SYS_CACHELINE_SIZE;
 	}
 
-	asm("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0));
+	asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
 }
 
 void flush_cache(unsigned long start, unsigned long size)
@@ -114,8 +99,7 @@ void flush_cache(unsigned long start, unsigned long size)
 /*
  * Stub implementations for l2 cache operations
  */
-void __l2_cache_disable(void)
-{
-}
+void __l2_cache_disable(void) {}
+
 void l2_cache_disable(void)
-        __attribute__((weak, alias("__l2_cache_disable")));
+	__attribute__((weak, alias("__l2_cache_disable")));