X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fam33xx%2Fclock.c;h=d7d98d1111e0ed5495caa98045bbc5ab8bb897fc;hb=244044e151860b114c69c15e322ee3a5df3d5e1e;hp=bbb9c1353f211fd563c8bf1807c087f8662a60cc;hpb=e390e8709149664ff96cf19384264c84573f3082;p=u-boot

diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index bbb9c1353f..d7d98d1111 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -24,6 +24,7 @@
 
 #define PRCM_MOD_EN		0x2
 #define PRCM_FORCE_WAKEUP	0x2
+#define PRCM_FUNCTL		0x0
 
 #define PRCM_EMIF_CLK_ACTIVITY	BIT(2)
 #define PRCM_L3_GCLK_ACTIVITY	BIT(4)
@@ -38,11 +39,13 @@
 #define CLK_MODE_SEL		0x7
 #define CLK_MODE_MASK		0xfffffff8
 #define CLK_DIV_SEL		0xFFFFFFE0
-
+#define CPGMAC0_IDLE		0x30000
+#define DPLL_CLKDCOLDO_GATE_CTRL        0x300
 
 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
+const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
 
 static void enable_interface_clocks(void)
 {
@@ -70,6 +73,10 @@ static void enable_interface_clocks(void)
 	writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
 	while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
 		;
+
+	writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
+	while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
+		;
 }
 
 /*
@@ -109,6 +116,51 @@ static void enable_per_clocks(void)
 	while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
 		;
 
+	/* UART1 */
+#ifdef CONFIG_SERIAL2
+	writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
+	while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
+		;
+#endif /* CONFIG_SERIAL2 */
+
+	/* UART2 */
+#ifdef CONFIG_SERIAL3
+	writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
+	while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
+		;
+#endif /* CONFIG_SERIAL3 */
+
+	/* UART3 */
+#ifdef CONFIG_SERIAL4
+	writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
+	while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
+		;
+#endif /* CONFIG_SERIAL4 */
+
+	/* UART4 */
+#ifdef CONFIG_SERIAL5
+	writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
+	while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
+		;
+#endif /* CONFIG_SERIAL5 */
+
+	/* UART5 */
+#ifdef CONFIG_SERIAL6
+	writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
+	while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
+		;
+#endif /* CONFIG_SERIAL6 */
+
+	/* GPMC */
+	writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
+	while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
+		;
+
+	/* ELM */
+	writel(PRCM_MOD_EN, &cmper->elmclkctrl);
+	while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN)
+		;
+
 	/* MMC0*/
 	writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
 	while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
@@ -118,6 +170,46 @@ static void enable_per_clocks(void)
 	writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
 	while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
 		;
+
+	/* gpio1 module */
+	writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
+	while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
+		;
+
+	/* gpio2 module */
+	writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
+	while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
+		;
+
+	/* gpio3 module */
+	writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
+	while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
+		;
+
+	/* i2c1 */
+	writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
+	while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
+		;
+
+	/* Ethernet */
+	writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
+	while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
+		;
+
+	/* spi0 */
+	writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
+	while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
+		;
+
+	/* RTC */
+	writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
+	while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
+		;
+
+	/* MUSB */
+	writel(PRCM_MOD_EN, &cmper->usb0clkctrl);
+	while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN)
+		;
 }
 
 static void mpu_pll_config(void)
@@ -214,9 +306,11 @@ static void per_pll_config(void)
 
 	while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
 		;
+
+	writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
 }
 
-static void ddr_pll_config(void)
+void ddr_pll_config(unsigned int ddrpll_m)
 {
 	u32 clkmode, clksel, div_m2;
 
@@ -234,7 +328,7 @@ static void ddr_pll_config(void)
 		;
 
 	clksel = clksel & (~CLK_SEL_MASK);
-	clksel = clksel | ((DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N);
+	clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
 	writel(clksel, &cmwkup->clkseldpllddr);
 
 	div_m2 = div_m2 & CLK_DIV_SEL;
@@ -255,11 +349,6 @@ void enable_emif_clocks(void)
 	writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
 	/* Enable EMIF0 Clock */
 	writel(PRCM_MOD_EN, &cmper->emifclkctrl);
-	/* Poll for emif_gclk  & L3_G clock  are active */
-	while ((readl(&cmper->l3clkstctrl) & (PRCM_EMIF_CLK_ACTIVITY |
-			PRCM_L3_GCLK_ACTIVITY)) != (PRCM_EMIF_CLK_ACTIVITY |
-			PRCM_L3_GCLK_ACTIVITY))
-		;
 	/* Poll if module is functional */
 	while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
 		;
@@ -273,7 +362,6 @@ void pll_init()
 	mpu_pll_config();
 	core_pll_config();
 	per_pll_config();
-	ddr_pll_config();
 
 	/* Enable the required interconnect clocks */
 	enable_interface_clocks();