X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fcache_v7.c;h=e8ee875981f587ac8b32f537f80b76b92c660eef;hb=1131d4e22cf8f13d0dabaad7f1b84d9baffdfbd6;hp=0f9d8377ed5ac568d996257647c9137d6fa60477;hpb=256d83cd6d8caf345ffba414a0f77f30d68caf8a;p=u-boot

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 0f9d8377ed..e8ee875981 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -68,7 +68,7 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
 		}
 	}
 	/* DSB to make sure the operation is complete */
-	CP15DSB;
+	DSB;
 }
 
 static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
@@ -96,7 +96,7 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
 		}
 	}
 	/* DSB to make sure the operation is complete */
-	CP15DSB;
+	DSB;
 }
 
 static void v7_maint_dcache_level_setway(u32 level, u32 operation)
@@ -215,7 +215,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
 	}
 
 	/* DSB to make sure the operation is complete */
-	CP15DSB;
+	DSB;
 }
 
 /* Invalidate TLB */
@@ -228,9 +228,9 @@ static void v7_inval_tlb(void)
 	/* Invalidate entire instruction TLB */
 	asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
 	/* Full system DSB - make sure that the invalidation is complete */
-	CP15DSB;
+	DSB;
 	/* Full system ISB - make sure the instruction stream sees it */
-	CP15ISB;
+	ISB;
 }
 
 void invalidate_dcache_all(void)
@@ -343,10 +343,10 @@ void invalidate_icache_all(void)
 	asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
 
 	/* Full system DSB - make sure that the invalidation is complete */
-	CP15DSB;
+	DSB;
 
 	/* ISB - make sure the instruction stream sees it */
-	CP15ISB;
+	ISB;
 }
 #else
 void invalidate_icache_all(void)