X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fexynos%2Fclock.c;h=1fea4d66639870faa1d869f4caa1e3c057abe3da;hb=bcb879c0e37db1cf527ff408df93918f155012ea;hp=74599798c435ff84ee4e05117c13936e57351ed7;hpb=7528cf5f016b5b8b8b12b373f6f31a10bf89233d;p=u-boot diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 74599798c4..1fea4d6663 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -2,23 +2,7 @@ * Copyright (C) 2010 Samsung Electronics * Minkyu Kang * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -27,6 +11,53 @@ #include #include +#define PLL_DIV_1024 1024 +#define PLL_DIV_65535 65535 +#define PLL_DIV_65536 65536 + +/* * + * This structure is to store the src bit, div bit and prediv bit + * positions of the peripheral clocks of the src and div registers + */ +struct clk_bit_info { + int8_t src_bit; + int8_t div_bit; + int8_t prediv_bit; +}; + +/* src_bit div_bit prediv_bit */ +static struct clk_bit_info clk_bit_info[] = { + {0, 0, -1}, + {4, 4, -1}, + {8, 8, -1}, + {12, 12, -1}, + {0, 0, 8}, + {4, 16, 24}, + {8, 0, 8}, + {12, 16, 24}, + {-1, -1, -1}, + {16, 0, 8}, + {20, 16, 24}, + {24, 0, 8}, + {0, 0, 4}, + {4, 12, 16}, + {-1, -1, -1}, + {-1, -1, -1}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, +}; + /* Epll Clock division values to achive different frequency output */ static struct set_epll_con_val exynos5_epll_div[] = { { 192000000, 0, 48, 3, 1, 0 }, @@ -42,6 +73,7 @@ static struct set_epll_con_val exynos5_epll_div[] = { static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) { unsigned long m, p, s = 0, mask, fout; + unsigned int div; unsigned int freq; /* * APLL_CON: MIDV [25:16] @@ -64,21 +96,46 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) freq = CONFIG_SYS_CLK_FREQ; - if (pllreg == EPLL) { + if (pllreg == EPLL || pllreg == RPLL) { k = k & 0xffff; /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ - fout = (m + k / 65536) * (freq / (p * (1 << s))); + fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s))); } else if (pllreg == VPLL) { k = k & 0xfff; - /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */ - fout = (m + k / 1024) * (freq / (p * (1 << s))); + + /* + * Exynos4210 + * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) + * + * Exynos4412 + * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV) + * + * Exynos5250 + * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) + */ + if (proid_is_exynos4210()) + div = PLL_DIV_1024; + else if (proid_is_exynos4412()) + div = PLL_DIV_65535; + else if (proid_is_exynos5250() || proid_is_exynos5420()) + div = PLL_DIV_65536; + else + return 0; + + fout = (m + k / div) * (freq / (p * (1 << s))); } else { - if (s < 1) - s = 1; - /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */ - fout = m * (freq / (p * (1 << (s - 1)))); + /* + * Exynos4412 / Exynos5250 + * FOUT = MDIV * FIN / (PDIV * 2^SDIV) + * + * Exynos4210 + * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1)) + */ + if (proid_is_exynos4210()) + fout = m * (freq / (p * (1 << (s - 1)))); + else + fout = m * (freq / (p * (1 << s))); } - return fout; } @@ -112,6 +169,36 @@ static unsigned long exynos4_get_pll_clk(int pllreg) return exynos_get_pll_clk(pllreg, r, k); } +/* exynos4x12: return pll clock frequency */ +static unsigned long exynos4x12_get_pll_clk(int pllreg) +{ + struct exynos4x12_clock *clk = + (struct exynos4x12_clock *)samsung_get_base_clock(); + unsigned long r, k = 0; + + switch (pllreg) { + case APLL: + r = readl(&clk->apll_con0); + break; + case MPLL: + r = readl(&clk->mpll_con0); + break; + case EPLL: + r = readl(&clk->epll_con0); + k = readl(&clk->epll_con1); + break; + case VPLL: + r = readl(&clk->vpll_con0); + k = readl(&clk->vpll_con1); + break; + default: + printf("Unsupported PLL (%d)\n", pllreg); + return 0; + } + + return exynos_get_pll_clk(pllreg, r, k); +} + /* exynos5: return pll clock frequency */ static unsigned long exynos5_get_pll_clk(int pllreg) { @@ -171,6 +258,147 @@ static unsigned long exynos5_get_pll_clk(int pllreg) return fout; } +static unsigned long exynos5_get_periph_rate(int peripheral) +{ + struct clk_bit_info *bit_info = &clk_bit_info[peripheral]; + unsigned long sclk, sub_clk; + unsigned int src, div, sub_div; + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + src = readl(&clk->src_peric0); + div = readl(&clk->div_peric0); + break; + case PERIPH_ID_PWM0: + case PERIPH_ID_PWM1: + case PERIPH_ID_PWM2: + case PERIPH_ID_PWM3: + case PERIPH_ID_PWM4: + src = readl(&clk->src_peric0); + div = readl(&clk->div_peric3); + break; + case PERIPH_ID_I2S0: + src = readl(&clk->src_mau); + div = readl(&clk->div_mau); + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + src = readl(&clk->src_peric1); + div = readl(&clk->div_peric1); + break; + case PERIPH_ID_SPI2: + src = readl(&clk->src_peric1); + div = readl(&clk->div_peric2); + break; + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + src = readl(&clk->sclk_src_isp); + div = readl(&clk->sclk_div_isp); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC2: + case PERIPH_ID_SDMMC3: + src = readl(&clk->src_fsys); + div = readl(&clk->div_fsys1); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + sclk = exynos5_get_pll_clk(MPLL); + sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit) + & 0x7) + 1; + div = ((readl(&clk->div_top0) >> bit_info->prediv_bit) + & 0x7) + 1; + return (sclk / sub_div) / div; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + }; + + src = (src >> bit_info->src_bit) & 0xf; + + switch (src) { + case EXYNOS_SRC_MPLL: + sclk = exynos5_get_pll_clk(MPLL); + break; + case EXYNOS_SRC_EPLL: + sclk = exynos5_get_pll_clk(EPLL); + break; + case EXYNOS_SRC_VPLL: + sclk = exynos5_get_pll_clk(VPLL); + break; + default: + return 0; + } + + /* Ratio clock division for this peripheral */ + sub_div = (div >> bit_info->div_bit) & 0xf; + sub_clk = sclk / (sub_div + 1); + + /* Pre-ratio clock division for SDMMC0 and 2 */ + if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) { + div = (div >> bit_info->prediv_bit) & 0xff; + return sub_clk / (div + 1); + } + + return sub_clk; +} + +unsigned long clock_get_periph_rate(int peripheral) +{ + if (cpu_is_exynos5()) + return exynos5_get_periph_rate(peripheral); + else + return 0; +} + +/* exynos5420: return pll clock frequency */ +static unsigned long exynos5420_get_pll_clk(int pllreg) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long r, k = 0; + + switch (pllreg) { + case APLL: + r = readl(&clk->apll_con0); + break; + case MPLL: + r = readl(&clk->mpll_con0); + break; + case EPLL: + r = readl(&clk->epll_con0); + k = readl(&clk->epll_con1); + break; + case VPLL: + r = readl(&clk->vpll_con0); + k = readl(&clk->vpll_con1); + break; + case BPLL: + r = readl(&clk->bpll_con0); + break; + case RPLL: + r = readl(&clk->rpll_con0); + k = readl(&clk->rpll_con1); + break; + default: + printf("Unsupported PLL (%d)\n", pllreg); + return 0; + } + + return exynos_get_pll_clk(pllreg, r, k); +} + /* exynos4: return ARM clock frequency */ static unsigned long exynos4_get_arm_clk(void) { @@ -193,6 +421,28 @@ static unsigned long exynos4_get_arm_clk(void) return armclk; } +/* exynos4x12: return ARM clock frequency */ +static unsigned long exynos4x12_get_arm_clk(void) +{ + struct exynos4x12_clock *clk = + (struct exynos4x12_clock *)samsung_get_base_clock(); + unsigned long div; + unsigned long armclk; + unsigned int core_ratio; + unsigned int core2_ratio; + + div = readl(&clk->div_cpu0); + + /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */ + core_ratio = (div >> 0) & 0x7; + core2_ratio = (div >> 28) & 0x7; + + armclk = get_pll_clk(APLL) / (core_ratio + 1); + armclk /= (core2_ratio + 1); + + return armclk; +} + /* exynos5: return ARM clock frequency */ static unsigned long exynos5_get_arm_clk(void) { @@ -258,20 +508,34 @@ static unsigned long exynos4_get_pwm_clk(void) return pclk; } -/* exynos5: return pwm clock frequency */ -static unsigned long exynos5_get_pwm_clk(void) +/* exynos4x12: return pwm clock frequency */ +static unsigned long exynos4x12_get_pwm_clk(void) { - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); + unsigned long pclk, sclk; + unsigned int ratio; + + sclk = get_pll_clk(MPLL); + ratio = 8; + + pclk = sclk / (ratio + 1); + + return pclk; +} + +/* exynos5420: return pwm clock frequency */ +static unsigned long exynos5420_get_pwm_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); unsigned long pclk, sclk; unsigned int ratio; /* - * CLK_DIV_PERIC3 - * PWM_RATIO [3:0] + * CLK_DIV_PERIC0 + * PWM_RATIO [31:28] */ - ratio = readl(&clk->div_peric3); - ratio = ratio & 0xf; + ratio = readl(&clk->div_peric0); + ratio = (ratio >> 28) & 0xf; sclk = get_pll_clk(MPLL); pclk = sclk / (ratio + 1); @@ -326,6 +590,51 @@ static unsigned long exynos4_get_uart_clk(int dev_index) return uclk; } +/* exynos4x12: return uart clock frequency */ +static unsigned long exynos4x12_get_uart_clk(int dev_index) +{ + struct exynos4x12_clock *clk = + (struct exynos4x12_clock *)samsung_get_base_clock(); + unsigned long uclk, sclk; + unsigned int sel; + unsigned int ratio; + + /* + * CLK_SRC_PERIL0 + * UART0_SEL [3:0] + * UART1_SEL [7:4] + * UART2_SEL [8:11] + * UART3_SEL [12:15] + * UART4_SEL [16:19] + */ + sel = readl(&clk->src_peril0); + sel = (sel >> (dev_index << 2)) & 0xf; + + if (sel == 0x6) + sclk = get_pll_clk(MPLL); + else if (sel == 0x7) + sclk = get_pll_clk(EPLL); + else if (sel == 0x8) + sclk = get_pll_clk(VPLL); + else + return 0; + + /* + * CLK_DIV_PERIL0 + * UART0_RATIO [3:0] + * UART1_RATIO [7:4] + * UART2_RATIO [8:11] + * UART3_RATIO [12:15] + * UART4_RATIO [16:19] + */ + ratio = readl(&clk->div_peril0); + ratio = (ratio >> (dev_index << 2)) & 0xf; + + uclk = sclk / (ratio + 1); + + return uclk; +} + /* exynos5: return uart clock frequency */ static unsigned long exynos5_get_uart_clk(int dev_index) { @@ -373,31 +682,239 @@ static unsigned long exynos5_get_uart_clk(int dev_index) return uclk; } +/* exynos5420: return uart clock frequency */ +static unsigned long exynos5420_get_uart_clk(int dev_index) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long uclk, sclk; + unsigned int sel; + unsigned int ratio; + + /* + * CLK_SRC_PERIC0 + * UART0_SEL [6:4] + * UART1_SEL [10:8] + * UART2_SEL [14:12] + * UART3_SEL [18:16] + * generalised calculation as follows + * sel = (sel >> ((dev_index * 4) + 4)) & mask; + */ + sel = readl(&clk->src_peric0); + sel = (sel >> ((dev_index * 4) + 4)) & 0x7; + + if (sel == 0x3) + sclk = get_pll_clk(MPLL); + else if (sel == 0x6) + sclk = get_pll_clk(EPLL); + else if (sel == 0x7) + sclk = get_pll_clk(RPLL); + else + return 0; + + /* + * CLK_DIV_PERIC0 + * UART0_RATIO [11:8] + * UART1_RATIO [15:12] + * UART2_RATIO [19:16] + * UART3_RATIO [23:20] + * generalised calculation as follows + * ratio = (ratio >> ((dev_index * 4) + 8)) & mask; + */ + ratio = readl(&clk->div_peric0); + ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf; + + uclk = sclk / (ratio + 1); + + return uclk; +} + +static unsigned long exynos4_get_mmc_clk(int dev_index) +{ + struct exynos4_clock *clk = + (struct exynos4_clock *)samsung_get_base_clock(); + unsigned long uclk, sclk; + unsigned int sel, ratio, pre_ratio; + int shift = 0; + + sel = readl(&clk->src_fsys); + sel = (sel >> (dev_index << 2)) & 0xf; + + if (sel == 0x6) + sclk = get_pll_clk(MPLL); + else if (sel == 0x7) + sclk = get_pll_clk(EPLL); + else if (sel == 0x8) + sclk = get_pll_clk(VPLL); + else + return 0; + + switch (dev_index) { + case 0: + case 1: + ratio = readl(&clk->div_fsys1); + pre_ratio = readl(&clk->div_fsys1); + break; + case 2: + case 3: + ratio = readl(&clk->div_fsys2); + pre_ratio = readl(&clk->div_fsys2); + break; + case 4: + ratio = readl(&clk->div_fsys3); + pre_ratio = readl(&clk->div_fsys3); + break; + default: + return 0; + } + + if (dev_index == 1 || dev_index == 3) + shift = 16; + + ratio = (ratio >> shift) & 0xf; + pre_ratio = (pre_ratio >> (shift + 8)) & 0xff; + uclk = (sclk / (ratio + 1)) / (pre_ratio + 1); + + return uclk; +} + +static unsigned long exynos5_get_mmc_clk(int dev_index) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned long uclk, sclk; + unsigned int sel, ratio, pre_ratio; + int shift = 0; + + sel = readl(&clk->src_fsys); + sel = (sel >> (dev_index << 2)) & 0xf; + + if (sel == 0x6) + sclk = get_pll_clk(MPLL); + else if (sel == 0x7) + sclk = get_pll_clk(EPLL); + else if (sel == 0x8) + sclk = get_pll_clk(VPLL); + else + return 0; + + switch (dev_index) { + case 0: + case 1: + ratio = readl(&clk->div_fsys1); + pre_ratio = readl(&clk->div_fsys1); + break; + case 2: + case 3: + ratio = readl(&clk->div_fsys2); + pre_ratio = readl(&clk->div_fsys2); + break; + default: + return 0; + } + + if (dev_index == 1 || dev_index == 3) + shift = 16; + + ratio = (ratio >> shift) & 0xf; + pre_ratio = (pre_ratio >> (shift + 8)) & 0xff; + uclk = (sclk / (ratio + 1)) / (pre_ratio + 1); + + return uclk; +} + +static unsigned long exynos5420_get_mmc_clk(int dev_index) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long uclk, sclk; + unsigned int sel, ratio; + + /* + * CLK_SRC_FSYS + * MMC0_SEL [10:8] + * MMC1_SEL [14:12] + * MMC2_SEL [18:16] + * generalised calculation as follows + * sel = (sel >> ((dev_index * 4) + 8)) & mask + */ + sel = readl(&clk->src_fsys); + sel = (sel >> ((dev_index * 4) + 8)) & 0x7; + + if (sel == 0x3) + sclk = get_pll_clk(MPLL); + else if (sel == 0x6) + sclk = get_pll_clk(EPLL); + else + return 0; + + /* + * CLK_DIV_FSYS1 + * MMC0_RATIO [9:0] + * MMC1_RATIO [19:10] + * MMC2_RATIO [29:20] + * generalised calculation as follows + * ratio = (ratio >> (dev_index * 10)) & mask + */ + ratio = readl(&clk->div_fsys1); + ratio = (ratio >> (dev_index * 10)) & 0x3ff; + + uclk = (sclk / (ratio + 1)); + + return uclk; +} + /* exynos4: set the mmc clock */ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) { struct exynos4_clock *clk = (struct exynos4_clock *)samsung_get_base_clock(); unsigned int addr; - unsigned int val; /* * CLK_DIV_FSYS1 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24] * CLK_DIV_FSYS2 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] + * CLK_DIV_FSYS3 + * MMC4_PRE_RATIO [15:8] */ if (dev_index < 2) { addr = (unsigned int)&clk->div_fsys1; + } else if (dev_index == 4) { + addr = (unsigned int)&clk->div_fsys3; + dev_index -= 4; } else { addr = (unsigned int)&clk->div_fsys2; dev_index -= 2; } - val = readl(addr); - val &= ~(0xff << ((dev_index << 4) + 8)); - val |= (div & 0xff) << ((dev_index << 4) + 8); - writel(val, addr); + clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), + (div & 0xff) << ((dev_index << 4) + 8)); +} + +/* exynos4x12: set the mmc clock */ +static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div) +{ + struct exynos4x12_clock *clk = + (struct exynos4x12_clock *)samsung_get_base_clock(); + unsigned int addr; + + /* + * CLK_DIV_FSYS1 + * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24] + * CLK_DIV_FSYS2 + * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] + */ + if (dev_index < 2) { + addr = (unsigned int)&clk->div_fsys1; + } else { + addr = (unsigned int)&clk->div_fsys2; + dev_index -= 2; + } + + clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), + (div & 0xff) << ((dev_index << 4) + 8)); } /* exynos5: set the mmc clock */ @@ -406,7 +923,6 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); unsigned int addr; - unsigned int val; /* * CLK_DIV_FSYS1 @@ -421,10 +937,28 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) dev_index -= 2; } - val = readl(addr); - val &= ~(0xff << ((dev_index << 4) + 8)); - val |= (div & 0xff) << ((dev_index << 4) + 8); - writel(val, addr); + clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), + (div & 0xff) << ((dev_index << 4) + 8)); +} + +/* exynos5: set the mmc clock */ +static void exynos5420_set_mmc_clk(int dev_index, unsigned int div) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned int addr; + unsigned int shift; + + /* + * CLK_DIV_FSYS1 + * MMC0_RATIO [9:0] + * MMC1_RATIO [19:10] + * MMC2_RATIO [29:20] + */ + addr = (unsigned int)&clk->div_fsys1; + shift = dev_index * 10; + + clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift); } /* get_lcd_clk: return lcd clock frequency */ @@ -515,7 +1049,6 @@ void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = (struct exynos4_clock *)samsung_get_base_clock(); - unsigned int cfg = 0; /* * CLK_GATE_BLOCK @@ -527,9 +1060,7 @@ void exynos4_set_lcd_clk(void) * CLK_LCD1 [5] * CLK_GPS [7] */ - cfg = readl(&clk->gate_block); - cfg |= 1 << 4; - writel(cfg, &clk->gate_block); + setbits_le32(&clk->gate_block, 1 << 4); /* * CLK_SRC_LCD0 @@ -539,10 +1070,7 @@ void exynos4_set_lcd_clk(void) * MIPI0_SEL [12:15] * set lcd0 src clock 0x6: SCLK_MPLL */ - cfg = readl(&clk->src_lcd0); - cfg &= ~(0xf); - cfg |= 0x6; - writel(cfg, &clk->src_lcd0); + clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6); /* * CLK_GATE_IP_LCD0 @@ -554,9 +1082,7 @@ void exynos4_set_lcd_clk(void) * CLK_PPMULCD0 [5] * Gating all clocks for FIMD0 */ - cfg = readl(&clk->gate_ip_lcd0); - cfg |= 1 << 0; - writel(cfg, &clk->gate_ip_lcd0); + setbits_le32(&clk->gate_ip_lcd0, 1 << 0); /* * CLK_DIV_LCD0 @@ -568,16 +1094,13 @@ void exynos4_set_lcd_clk(void) * MIPI0_PRE_RATIO [23:20] * set fimd ratio */ - cfg &= ~(0xf); - cfg |= 0x1; - writel(cfg, &clk->div_lcd0); + clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1); } void exynos5_set_lcd_clk(void) { struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); - unsigned int cfg = 0; /* * CLK_GATE_BLOCK @@ -589,9 +1112,7 @@ void exynos5_set_lcd_clk(void) * CLK_LCD1 [5] * CLK_GPS [7] */ - cfg = readl(&clk->gate_block); - cfg |= 1 << 4; - writel(cfg, &clk->gate_block); + setbits_le32(&clk->gate_block, 1 << 4); /* * CLK_SRC_LCD0 @@ -601,10 +1122,7 @@ void exynos5_set_lcd_clk(void) * MIPI0_SEL [12:15] * set lcd0 src clock 0x6: SCLK_MPLL */ - cfg = readl(&clk->src_disp1_0); - cfg &= ~(0xf); - cfg |= 0x8; - writel(cfg, &clk->src_disp1_0); + clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6); /* * CLK_GATE_IP_LCD0 @@ -616,9 +1134,7 @@ void exynos5_set_lcd_clk(void) * CLK_PPMULCD0 [5] * Gating all clocks for FIMD0 */ - cfg = readl(&clk->gate_ip_disp1); - cfg |= 1 << 0; - writel(cfg, &clk->gate_ip_disp1); + setbits_le32(&clk->gate_ip_disp1, 1 << 0); /* * CLK_DIV_LCD0 @@ -630,16 +1146,13 @@ void exynos5_set_lcd_clk(void) * MIPI0_PRE_RATIO [23:20] * set fimd ratio */ - cfg &= ~(0xf); - cfg |= 0x0; - writel(cfg, &clk->div_disp1_0); + clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0); } void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = (struct exynos4_clock *)samsung_get_base_clock(); - unsigned int cfg = 0; /* * CLK_SRC_LCD0 @@ -649,10 +1162,7 @@ void exynos4_set_mipi_clk(void) * MIPI0_SEL [12:15] * set mipi0 src clock 0x6: SCLK_MPLL */ - cfg = readl(&clk->src_lcd0); - cfg &= ~(0xf << 12); - cfg |= (0x6 << 12); - writel(cfg, &clk->src_lcd0); + clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12); /* * CLK_SRC_MASK_LCD0 @@ -662,9 +1172,7 @@ void exynos4_set_mipi_clk(void) * MIPI0_MASK [12] * set src mask mipi0 0x1: Unmask */ - cfg = readl(&clk->src_mask_lcd0); - cfg |= (0x1 << 12); - writel(cfg, &clk->src_mask_lcd0); + setbits_le32(&clk->src_mask_lcd0, 0x1 << 12); /* * CLK_GATE_IP_LCD0 @@ -676,9 +1184,7 @@ void exynos4_set_mipi_clk(void) * CLK_PPMULCD0 [5] * Gating all clocks for MIPI0 */ - cfg = readl(&clk->gate_ip_lcd0); - cfg |= 1 << 3; - writel(cfg, &clk->gate_ip_lcd0); + setbits_le32(&clk->gate_ip_lcd0, 1 << 3); /* * CLK_DIV_LCD0 @@ -690,9 +1196,7 @@ void exynos4_set_mipi_clk(void) * MIPI0_PRE_RATIO [23:20] * set mipi ratio */ - cfg &= ~(0xf << 16); - cfg |= (0x1 << 16); - writel(cfg, &clk->div_lcd0); + clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16); } /* @@ -772,17 +1276,29 @@ int exynos5_set_epll_clk(unsigned long rate) return 0; } -void exynos5_set_i2s_clk_source(void) +int exynos5_set_i2s_clk_source(unsigned int i2s_id) { struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); - - clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK, - (CLK_SRC_SCLK_EPLL)); + unsigned int *audio_ass = (unsigned int *)samsung_get_base_audio_ass(); + + if (i2s_id == 0) { + setbits_le32(&clk->src_top2, CLK_SRC_MOUT_EPLL); + clrsetbits_le32(&clk->src_mau, AUDIO0_SEL_MASK, + (CLK_SRC_SCLK_EPLL)); + setbits_le32(audio_ass, AUDIO_CLKMUX_ASS); + } else if (i2s_id == 1) { + clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK, + (CLK_SRC_SCLK_EPLL)); + } else { + return -1; + } + return 0; } int exynos5_set_i2s_clk_prescaler(unsigned int src_frq, - unsigned int dst_frq) + unsigned int dst_frq, + unsigned int i2s_id) { struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); @@ -795,13 +1311,27 @@ int exynos5_set_i2s_clk_prescaler(unsigned int src_frq, } div = (src_frq / dst_frq); - if (div > AUDIO_1_RATIO_MASK) { - debug("%s: Frequency ratio is out of range\n", __func__); - debug("src frq = %d des frq = %d ", src_frq, dst_frq); + if (i2s_id == 0) { + if (div > AUDIO_0_RATIO_MASK) { + debug("%s: Frequency ratio is out of range\n", + __func__); + debug("src frq = %d des frq = %d ", src_frq, dst_frq); + return -1; + } + clrsetbits_le32(&clk->div_mau, AUDIO_0_RATIO_MASK, + (div & AUDIO_0_RATIO_MASK)); + } else if(i2s_id == 1) { + if (div > AUDIO_1_RATIO_MASK) { + debug("%s: Frequency ratio is out of range\n", + __func__); + debug("src frq = %d des frq = %d ", src_frq, dst_frq); + return -1; + } + clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK, + (div & AUDIO_1_RATIO_MASK)); + } else { return -1; } - clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK, - (div & AUDIO_1_RATIO_MASK)); return 0; } @@ -921,6 +1451,71 @@ static int exynos5_set_spi_clk(enum periph_id periph_id, return 0; } +static int exynos5420_set_spi_clk(enum periph_id periph_id, + unsigned int rate) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + int main; + unsigned int fine; + unsigned shift, pre_shift; + unsigned div_mask = 0xf, pre_div_mask = 0xff; + u32 *reg; + u32 *pre_reg; + + main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine); + if (main < 0) { + debug("%s: Cannot set clock rate for periph %d", + __func__, periph_id); + return -1; + } + main = main - 1; + fine = fine - 1; + + switch (periph_id) { + case PERIPH_ID_SPI0: + reg = &clk->div_peric1; + shift = 20; + pre_reg = &clk->div_peric4; + pre_shift = 8; + break; + case PERIPH_ID_SPI1: + reg = &clk->div_peric1; + shift = 24; + pre_reg = &clk->div_peric4; + pre_shift = 16; + break; + case PERIPH_ID_SPI2: + reg = &clk->div_peric1; + shift = 28; + pre_reg = &clk->div_peric4; + pre_shift = 24; + break; + case PERIPH_ID_SPI3: + reg = &clk->div_isp1; + shift = 16; + pre_reg = &clk->div_isp1; + pre_shift = 0; + break; + case PERIPH_ID_SPI4: + reg = &clk->div_isp1; + shift = 20; + pre_reg = &clk->div_isp1; + pre_shift = 8; + break; + default: + debug("%s: Unsupported peripheral ID %d\n", __func__, + periph_id); + return -1; + } + + clrsetbits_le32(reg, div_mask << shift, (main & div_mask) << shift); + clrsetbits_le32(pre_reg, pre_div_mask << pre_shift, + (fine & pre_div_mask) << pre_shift); + + return 0; +} + static unsigned long exynos4_get_i2c_clk(void) { struct exynos4_clock *clk = @@ -938,18 +1533,26 @@ static unsigned long exynos4_get_i2c_clk(void) unsigned long get_pll_clk(int pllreg) { - if (cpu_is_exynos5()) + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) + return exynos5420_get_pll_clk(pllreg); return exynos5_get_pll_clk(pllreg); - else + } else { + if (proid_is_exynos4412()) + return exynos4x12_get_pll_clk(pllreg); return exynos4_get_pll_clk(pllreg); + } } unsigned long get_arm_clk(void) { if (cpu_is_exynos5()) return exynos5_get_arm_clk(); - else + else { + if (proid_is_exynos4412()) + return exynos4x12_get_arm_clk(); return exynos4_get_arm_clk(); + } } unsigned long get_i2c_clk(void) @@ -966,26 +1569,54 @@ unsigned long get_i2c_clk(void) unsigned long get_pwm_clk(void) { - if (cpu_is_exynos5()) - return exynos5_get_pwm_clk(); - else + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) + return exynos5420_get_pwm_clk(); + return clock_get_periph_rate(PERIPH_ID_PWM0); + } else { + if (proid_is_exynos4412()) + return exynos4x12_get_pwm_clk(); return exynos4_get_pwm_clk(); + } } unsigned long get_uart_clk(int dev_index) { - if (cpu_is_exynos5()) + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) + return exynos5420_get_uart_clk(dev_index); return exynos5_get_uart_clk(dev_index); - else + } else { + if (proid_is_exynos4412()) + return exynos4x12_get_uart_clk(dev_index); return exynos4_get_uart_clk(dev_index); + } +} + +unsigned long get_mmc_clk(int dev_index) +{ + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) + return exynos5420_get_mmc_clk(dev_index); + return exynos5_get_mmc_clk(dev_index); + } else { + return exynos4_get_mmc_clk(dev_index); + } } void set_mmc_clk(int dev_index, unsigned int div) { - if (cpu_is_exynos5()) - exynos5_set_mmc_clk(dev_index, div); - else - exynos4_set_mmc_clk(dev_index, div); + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) + exynos5420_set_mmc_clk(dev_index, div); + else + exynos5_set_mmc_clk(dev_index, div); + } else { + if (proid_is_exynos4412()) + exynos4x12_set_mmc_clk(dev_index, div); + else + exynos4_set_mmc_clk(dev_index, div); + } } unsigned long get_lcd_clk(void) @@ -1012,25 +1643,30 @@ void set_mipi_clk(void) int set_spi_clk(int periph_id, unsigned int rate) { - if (cpu_is_exynos5()) + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) + return exynos5420_set_spi_clk(periph_id, rate); return exynos5_set_spi_clk(periph_id, rate); - else + } else { return 0; + } } -int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq) +int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq, + unsigned int i2s_id) { - if (cpu_is_exynos5()) - return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq); + return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq, i2s_id); else return 0; } -void set_i2s_clk_source(void) +int set_i2s_clk_source(unsigned int i2s_id) { if (cpu_is_exynos5()) - exynos5_set_i2s_clk_source(); + return exynos5_set_i2s_clk_source(i2s_id); + else + return 0; } int set_epll_clk(unsigned long rate)