X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fexynos%2Fcommon_setup.h;h=5235abb808a42c1a6b9ce6a90fd4eb53da5f139e;hb=0467faf555022fa5447a037b753b150448217239;hp=e6318c036679b2cf64f8a909c2853d4814cef2e1;hpb=630aacb0859c6e26b2b0311d8e245da5e5b8ac67;p=u-boot

diff --git a/arch/arm/cpu/armv7/exynos/common_setup.h b/arch/arm/cpu/armv7/exynos/common_setup.h
index e6318c0366..5235abb808 100644
--- a/arch/arm/cpu/armv7/exynos/common_setup.h
+++ b/arch/arm/cpu/armv7/exynos/common_setup.h
@@ -23,6 +23,8 @@
  * MA 02111-1307 USA
  */
 
+#include <asm/arch/system.h>
+
 #define DMC_OFFSET	0x10000
 
 /*
@@ -43,3 +45,63 @@ void system_clock_init(void);
 int do_lowlevel_init(void);
 
 void sdelay(unsigned long);
+
+enum l2_cache_params {
+	CACHE_DATA_RAM_LATENCY_2_CYCLES = (2 << 0),
+	CACHE_DATA_RAM_LATENCY_3_CYCLES = (3 << 0),
+	CACHE_DISABLE_CLEAN_EVICT = (1 << 3),
+	CACHE_DATA_RAM_SETUP = (1 << 5),
+	CACHE_TAG_RAM_LATENCY_2_CYCLES = (2 << 6),
+	CACHE_TAG_RAM_LATENCY_3_CYCLES = (3 << 6),
+	CACHE_ENABLE_HAZARD_DETECT = (1 << 7),
+	CACHE_TAG_RAM_SETUP = (1 << 9),
+	CACHE_ECC_AND_PARITY = (1 << 21),
+	CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27)
+};
+
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+/*
+ * Configure L2CTLR to get timings that keep us from hanging/crashing.
+ *
+ * Must be inline here since low_power_start() is called without a
+ * stack (!).
+ */
+static inline void configure_l2_ctlr(void)
+{
+	uint32_t val;
+
+	mrc_l2_ctlr(val);
+
+	val |= CACHE_TAG_RAM_SETUP |
+		CACHE_DATA_RAM_SETUP |
+		CACHE_TAG_RAM_LATENCY_2_CYCLES |
+		CACHE_DATA_RAM_LATENCY_2_CYCLES;
+
+	if (proid_is_exynos5420() || proid_is_exynos5800()) {
+		val |= CACHE_ECC_AND_PARITY |
+			CACHE_TAG_RAM_LATENCY_3_CYCLES |
+			CACHE_DATA_RAM_LATENCY_3_CYCLES;
+	}
+
+	mcr_l2_ctlr(val);
+}
+
+/*
+ * Configure L2ACTLR.
+ *
+ * Must be inline here since low_power_start() is called without a
+ * stack (!).
+ */
+static inline void configure_l2_actlr(void)
+{
+	uint32_t val;
+
+	if (proid_is_exynos5420() || proid_is_exynos5800()) {
+		mrc_l2_aux_ctlr(val);
+		val |= CACHE_ENABLE_FORCE_L2_LOGIC |
+			CACHE_DISABLE_CLEAN_EVICT;
+		mcr_l2_aux_ctlr(val);
+	}
+}
+#endif