X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fexynos%2Fexynos5_setup.h;h=9073f50f6b392ae6466d95bc917da4e72c986791;hb=f0f76b0a4c7181b2cbde39ec04eac8973cd4ad1f;hp=53b0ace6e3f7966699b6dda8cf0268a2dcaf703c;hpb=7f673c99c2d8d1aa21996c5b914f06d784b080ca;p=u-boot

diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
index 53b0ace6e3..9073f50f6b 100644
--- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
+++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
@@ -282,8 +282,12 @@
 #define PHY_CON12_VAL		0x10107F50
 #define CTRL_START		(1 << 6)
 #define CTRL_DLL_ON		(1 << 5)
+#define CTRL_LOCK_COARSE_OFFSET	10
+#define CTRL_LOCK_COARSE_MASK	(0x7F << CTRL_LOCK_COARSE_OFFSET)
+#define CTRL_LOCK_COARSE(x)	(((x) & CTRL_LOCK_COARSE_MASK) >> \
+				 CTRL_LOCK_COARSE_OFFSET)
 #define CTRL_FORCE_MASK		(0x7F << 8)
-#define CTRL_LOCK_COARSE_MASK	(0x7F << 10)
+#define CTRL_FINE_LOCKED	0x7
 
 #define CTRL_OFFSETD_RESET_VAL	0x8
 #define CTRL_OFFSETD_VAL	0x7F
@@ -431,10 +435,10 @@
 
 /*
  * Definitions that differ with SoC's.
- * Below is the part defining macros for smdk5250.
- * Else part introduces macros for smdk5420.
+ * Below is the part defining macros for Exynos5250.
+ * Else part introduces macros for Exynos5420.
  */
-#ifndef CONFIG_SMDK5420
+#ifndef CONFIG_EXYNOS5420
 
 /* APLL_CON1 */
 #define APLL_CON1_VAL	(0x00203800)
@@ -696,6 +700,9 @@
 #define CLK_DIV_CPERI1_VAL	NOT_AVAILABLE
 
 #else
+
+#define CPU_CONFIG_STATUS_OFFSET	0x80
+#define CPU_RST_FLAG_VAL		0xFCBA0D10
 #define PAD_RETENTION_DRAM_COREBLK_VAL	0x10000000
 
 /* APLL_CON1 */
@@ -779,7 +786,7 @@
 #define CLK_SRC_TOP2_VAL	0x11101000
 #define CLK_SRC_TOP3_VAL	0x11111111
 #define CLK_SRC_TOP4_VAL	0x11110111
-#define CLK_SRC_TOP5_VAL	0x11111100
+#define CLK_SRC_TOP5_VAL	0x11111101
 #define CLK_SRC_TOP6_VAL	0x11110111
 #define CLK_SRC_TOP7_VAL	0x00022200
 
@@ -890,16 +897,11 @@ enum {
 /*
  * Memory variant specific initialization code for DDR3
  *
- * @param mem		Memory timings for this memory type.
- * @param mem_iv_size	Memory interleaving size is a configurable parameter
- *			which the DMC uses to decide how to split a memory
- *			chunk into smaller chunks to support concurrent
- *			accesses; may vary across boards.
+ * @param mem          Memory timings for this memory type.
  * @param reset         Reset DDR PHY during initialization.
  * @return 0 if ok, SETUP_ERR_... if there is a problem
  */
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
-			int reset);
+int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset);
 
 /* Memory variant specific initialization code for LPDDR3 */
 void lpddr3_mem_ctrl_init(void);