X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fomap3%2Fboard.c;h=7d1f8d9d2c33758d6bdb3b9232dad562ff605248;hb=89993dc34afeeca4dad84e3c2db7403c406ccb78;hp=164069662f3aff2a541db5c7c4d8f0d32a9258a0;hpb=37189a19589794f8482a1c64dcebca2d6fbe96a5;p=u-boot diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 164069662f..7d1f8d9d2c 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -14,25 +14,10 @@ * Syed Mohammed Khasim * * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include #include #include @@ -40,13 +25,18 @@ #include #include #include +#include #include #include +DECLARE_GLOBAL_DATA_PTR; + /* Declarations */ extern omap3_sysinfo sysinfo; static void omap3_setup_aux_cr(void); +#ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_invalidate_l2_cache_secure(void); +#endif static const struct gpio_bank gpio_bank_34xx[6] = { { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX }, @@ -77,9 +67,6 @@ u32 spl_boot_mode(void) case BOOT_DEVICE_MMC1: return MMCSD_MODE_FAT; break; - case BOOT_DEVICE_NAND: - return NAND_MODE_HW_ECC; - break; default: puts("spl: ERROR: unknown device - can't select boot mode\n"); hang(); @@ -91,8 +78,25 @@ u32 spl_boot_device(void) return omap3_boot_device; } +int board_mmc_init(bd_t *bis) +{ + switch (spl_boot_device()) { + case BOOT_DEVICE_MMC1: + omap_mmc_init(0, 0, 0, -1, -1); + break; + case BOOT_DEVICE_MMC2: + case BOOT_DEVICE_MMC2_2: + omap_mmc_init(1, 0, 0, -1, -1); + break; + } + return 0; +} + void spl_board_init(void) { +#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT) + gpmc_init(); +#endif #ifdef CONFIG_SPL_I2C_SUPPORT i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif @@ -236,6 +240,8 @@ void s_init(void) #endif #ifdef CONFIG_SPL_BUILD + gd = &gdata; + preloader_console_init(); timer_init(); @@ -306,14 +312,25 @@ void abort(void) *****************************************************************************/ static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { - if (argc != 2) + if (argc < 2 || argc > 3) goto usage; - if (strncmp(argv[1], "hw", 2) == 0) - omap_nand_switch_ecc(1); - else if (strncmp(argv[1], "sw", 2) == 0) - omap_nand_switch_ecc(0); - else + + if (strncmp(argv[1], "hw", 2) == 0) { + if (argc == 2) { + omap_nand_switch_ecc(1, 1); + } else { + if (strncmp(argv[2], "hamming", 7) == 0) + omap_nand_switch_ecc(1, 1); + else if (strncmp(argv[2], "bch8", 4) == 0) + omap_nand_switch_ecc(1, 8); + else + goto usage; + } + } else if (strncmp(argv[1], "sw", 2) == 0) { + omap_nand_switch_ecc(0, 0); + } else { goto usage; + } return 0; @@ -323,9 +340,13 @@ usage: } U_BOOT_CMD( - nandecc, 2, 1, do_switch_ecc, + nandecc, 3, 1, do_switch_ecc, "switch OMAP3 NAND ECC calculation algorithm", - "[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm" + "hw [hamming|bch8] - Switch between NAND hardware 1-bit hamming and" + " 8-bit BCH\n" + " ecc calculation (second parameter may" + " be omitted).\n" + "nandecc sw - Switch to NAND software ecc algorithm." ); #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */ @@ -390,19 +411,6 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) } } -static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) -{ - u32 acr; - - /* Read ACR */ - asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); - acr &= ~clear_bits; - acr |= set_bits; - - /* Write ACR - affects non-secure banked bits */ - asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); -} - static void omap3_setup_aux_cr(void) { /* Workaround for Cortex-A8 errata: #454179 #430973 @@ -416,6 +424,19 @@ static void omap3_setup_aux_cr(void) } #ifndef CONFIG_SYS_L2CACHE_OFF +static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) +{ + u32 acr; + + /* Read ACR */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); + acr &= ~clear_bits; + acr |= set_bits; + + /* Write ACR - affects non-secure banked bits */ + asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); +} + /* Invalidate the entire L2 cache from secure mode */ static void omap3_invalidate_l2_cache_secure(void) { @@ -456,7 +477,7 @@ void omap3_outer_cache_disable(void) */ omap3_update_aux_cr(0, 0x2); } -#endif +#endif /* !CONFIG_SYS_L2CACHE_OFF */ #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) @@ -464,4 +485,4 @@ void enable_caches(void) /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); } -#endif +#endif /* !CONFIG_SYS_DCACHE_OFF */