X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fomap4%2Fhwinit.c;h=7c6638ca80dc30ac72cd743d9d80344c4d561808;hb=272686eb7576c02df4616bcf893fde993e7ba57e;hp=37a86b4c2f942b90a436c329648adce536a55580;hpb=1086c5d6f8541460f0f10e4a302d8aac27e0e6e0;p=u-boot diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index 37a86b4c2f..7c6638ca80 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -9,43 +9,28 @@ * Aneesh V * Steve Sakoman * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include #include -#include +#include #include #include +#include DECLARE_GLOBAL_DATA_PTR; -u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV; +u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV; static const struct gpio_bank gpio_bank_44xx[6] = { - { (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP44XX_GPIO1_BASE }, + { (void *)OMAP44XX_GPIO2_BASE }, + { (void *)OMAP44XX_GPIO3_BASE }, + { (void *)OMAP44XX_GPIO4_BASE }, + { (void *)OMAP44XX_GPIO5_BASE }, + { (void *)OMAP44XX_GPIO6_BASE }, }; const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx; @@ -57,10 +42,6 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx; void do_io_settings(void) { u32 lpddr2io; - struct control_lpddr2io_regs *lpddr2io_regs = - (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE; - struct omap4_sys_ctrl_regs *const ctrl = - (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE; u32 omap4_rev = omap_revision(); @@ -72,20 +53,20 @@ void do_io_settings(void) lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN; /* EMIF1 */ - writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0); - writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1); + writel(lpddr2io, (*ctrl)->control_lpddr2io1_0); + writel(lpddr2io, (*ctrl)->control_lpddr2io1_1); /* No pull for GR10 as per hw team's recommendation */ writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, - &lpddr2io_regs->control_lpddr2io1_2); - writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3); + (*ctrl)->control_lpddr2io1_2); + writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3); /* EMIF2 */ - writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0); - writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1); + writel(lpddr2io, (*ctrl)->control_lpddr2io2_0); + writel(lpddr2io, (*ctrl)->control_lpddr2io2_1); /* No pull for GR10 as per hw team's recommendation */ writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, - &lpddr2io_regs->control_lpddr2io2_2); - writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3); + (*ctrl)->control_lpddr2io2_2); + writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3); /* * Some of these settings (TRIM values) come from eFuse and are @@ -93,16 +74,16 @@ void do_io_settings(void) * calibration of the device. Do the software over-ride only if * the device is not correctly trimmed */ - if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) { + if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) { writel(LDOSRAM_VOLT_CTRL_OVERRIDE, - &ctrl->control_ldosram_iva_voltage_ctrl); + (*ctrl)->control_ldosram_iva_voltage_ctrl); writel(LDOSRAM_VOLT_CTRL_OVERRIDE, - &ctrl->control_ldosram_mpu_voltage_ctrl); + (*ctrl)->control_ldosram_mpu_voltage_ctrl); writel(LDOSRAM_VOLT_CTRL_OVERRIDE, - &ctrl->control_ldosram_core_voltage_ctrl); + (*ctrl)->control_ldosram_core_voltage_ctrl); } /* @@ -110,13 +91,18 @@ void do_io_settings(void) * i. unconditionally for all 4430 * ii. only if un-trimmed for 4460 */ - if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_1)) - writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1); + if (!readl((*ctrl)->control_efuse_1)) + writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1); + + if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2)) + writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2); +} +#endif /* CONFIG_SPL_BUILD */ - if (!readl(&ctrl->control_efuse_2)) - writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2); +/* dummy fuction for omap4 */ +void config_data_eye_leveling_samples(u32 emif_base) +{ } -#endif void init_omap_revision(void) { @@ -129,52 +115,63 @@ void init_omap_revision(void) switch (arm_rev) { case MIDR_CORTEX_A9_R0P1: - *omap4_revision = OMAP4430_ES1_0; + *omap_si_rev = OMAP4430_ES1_0; break; case MIDR_CORTEX_A9_R1P2: switch (readl(CONTROL_ID_CODE)) { case OMAP4_CONTROL_ID_CODE_ES2_0: - *omap4_revision = OMAP4430_ES2_0; + *omap_si_rev = OMAP4430_ES2_0; break; case OMAP4_CONTROL_ID_CODE_ES2_1: - *omap4_revision = OMAP4430_ES2_1; + *omap_si_rev = OMAP4430_ES2_1; break; case OMAP4_CONTROL_ID_CODE_ES2_2: - *omap4_revision = OMAP4430_ES2_2; + *omap_si_rev = OMAP4430_ES2_2; break; default: - *omap4_revision = OMAP4430_ES2_0; + *omap_si_rev = OMAP4430_ES2_0; break; } break; case MIDR_CORTEX_A9_R1P3: - *omap4_revision = OMAP4430_ES2_3; + *omap_si_rev = OMAP4430_ES2_3; break; case MIDR_CORTEX_A9_R2P10: switch (readl(CONTROL_ID_CODE)) { + case OMAP4470_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP4470_ES1_0; + break; case OMAP4460_CONTROL_ID_CODE_ES1_1: - *omap4_revision = OMAP4460_ES1_1; + *omap_si_rev = OMAP4460_ES1_1; break; case OMAP4460_CONTROL_ID_CODE_ES1_0: default: - *omap4_revision = OMAP4460_ES1_0; + *omap_si_rev = OMAP4460_ES1_0; break; } break; default: - *omap4_revision = OMAP4430_SILICON_ID_INVALID; + *omap_si_rev = OMAP4430_SILICON_ID_INVALID; break; } } +void omap_die_id(unsigned int *die_id) +{ + die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0); + die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1); + die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2); + die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3); +} + #ifndef CONFIG_SYS_L2CACHE_OFF void v7_outer_cache_enable(void) { - set_pl310_ctrl_reg(1); + omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1); } void v7_outer_cache_disable(void) { - set_pl310_ctrl_reg(0); + omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0); } -#endif +#endif /* !CONFIG_SYS_L2CACHE_OFF */