X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fstart.S;h=9b49ece2d650e199a1ed3415ed2ae47794f20fab;hb=b050898efa6b4f0272f12885a7365f044ab4c08e;hp=098a83ab7145bd324e6db9c20e0a5aea95c70970;hpb=942cb0b6a29f74507adeb0bce7ff7f23f69faf84;p=u-boot

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 098a83ab71..9b49ece2d6 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -54,8 +54,7 @@ save_boot_params_ret:
  * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
  * Continue to use ROM code vector only in OMAP4 spl)
  */
-#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) && \
-		!defined(CONFIG_SPL_FEL)
+#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
 	/* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
 	mrc	p15, 0, r0, c1, c0, 0	@ Read CP15 SCTLR Register
 	bic	r0, #CR_V		@ V = 0
@@ -68,9 +67,7 @@ save_boot_params_ret:
 
 	/* the mask ROM code should have PLL and others stable */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#ifndef CONFIG_SPL_FEL
 	bl	cpu_init_cp15
-#endif
 	bl	cpu_init_crit
 #endif