X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fstart.S;h=c0e184994abd729c3422750023620229956f3db3;hb=c5d4752c0541ea0af559250bd2bec6556fed6915;hp=d23dc9d719b926cc7f2e3b978fbc728d1df8a2e8;hpb=1086c5d6f8541460f0f10e4a302d8aac27e0e6e0;p=u-boot diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index d23dc9d719..c0e184994a 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -33,6 +33,7 @@ #include #include #include +#include .globl _start _start: b reset @@ -82,18 +83,6 @@ _end_vect: _TEXT_BASE: .word CONFIG_SYS_TEXT_BASE -#ifdef CONFIG_TEGRA2 -/* - * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s). - * U-Boot runs on the AVP first, setting things up for the CPU (PLLs, - * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU - * to pick up its reset vector, which points here. - */ -.globl _armboot_start -_armboot_start: - .word _start -#endif - /* * These are defined in the board-specific linker script. */ @@ -107,7 +96,7 @@ _image_copy_end_ofs: .globl _bss_end_ofs _bss_end_ofs: - .word __bss_end__ - _start + .word __bss_end - _start .globl _end_ofs _end_ofs: @@ -162,18 +151,15 @@ reset: /* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_cp15 bl cpu_init_crit #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ +#ifndef CONFIG_SPL_BUILD /* * void relocate_code (addr_sp, gd, addr_moni) * @@ -181,20 +167,15 @@ call_board_init_f: * after relocating the monitor code. * */ - .globl relocate_code -relocate_code: +ENTRY(relocate_code) mov r4, r0 /* save addr_sp */ mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -205,7 +186,6 @@ copy_loop: cmp r0, r2 /* until source end address [r2] */ blo copy_loop -#ifndef CONFIG_SPL_BUILD /* * fix .rel.dyn relocations */ @@ -244,40 +224,22 @@ fixnext: add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ cmp r2, r3 blo fixloop - b clear_bss + +relocate_done: + + bx lr + _rel_dyn_start_ofs: .word __rel_dyn_start - _start _rel_dyn_end_ofs: .word __rel_dyn_end - _start _dynsym_start_ofs: .word __dynsym_start - _start +ENDPROC(relocate_code) -#endif /* #ifndef CONFIG_SPL_BUILD */ - -clear_bss: -#ifdef CONFIG_SPL_BUILD - /* No relocation for SPL */ - ldr r0, =__bss_start - ldr r1, =__bss_end__ -#else - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 #endif - mov r2, #0x00000000 /* clear */ -clbss_l:str r2, [r0] /* clear loop... */ - add r0, r0, #4 - cmp r0, r1 - bne clbss_l - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -jump_2_ram: +ENTRY(c_runtime_cpu_setup) /* * If I-cache is enabled invalidate it */ @@ -286,30 +248,43 @@ jump_2_ram: mcr p15, 0, r0, c7, c10, 4 @ DSB mcr p15, 0, r0, c7, c5, 4 @ ISB #endif - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ - mov pc, lr +/* + * Move vector table + */ +#if !defined(CONFIG_TEGRA) + /* Set vector address in CP15 VBAR register */ + ldr r0, =_start + add r0, r0, r9 + mcr p15, 0, r0, c12, c0, 0 @Set VBAR +#endif /* !Tegra */ -_board_init_r_ofs: - .word board_init_r - _start + bx lr +ENDPROC(c_runtime_cpu_setup) -#ifndef CONFIG_SKIP_LOWLEVEL_INIT /************************************************************************* * - * CPU_init_critical registers + * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) + * __attribute__((weak)); * - * setup important registers - * setup memory timing + * Stack pointer is not yet initialized at this moment + * Don't save anything to stack even if compiled with -O0 * *************************************************************************/ -cpu_init_crit: +ENTRY(save_boot_params) + bx lr @ back to my caller +ENDPROC(save_boot_params) + .weak save_boot_params + +/************************************************************************* + * + * cpu_init_cp15 + * + * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless + * CONFIG_SYS_ICACHE_OFF is defined. + * + *************************************************************************/ +ENTRY(cpu_init_cp15) /* * Invalidate L1 I/D */ @@ -335,16 +310,51 @@ cpu_init_crit: #endif mcr p15, 0, r0, c1, c0, 0 +#ifdef CONFIG_ARM_ERRATA_716044 + mrc p15, 0, r0, c1, c0, 0 @ read system control register + orr r0, r0, #1 << 11 @ set bit #11 + mcr p15, 0, r0, c1, c0, 0 @ write system control register +#endif + +#ifdef CONFIG_ARM_ERRATA_742230 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 4 @ set bit #4 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif + +#ifdef CONFIG_ARM_ERRATA_743622 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 6 @ set bit #6 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif + +#ifdef CONFIG_ARM_ERRATA_751472 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 11 @ set bit #11 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif + + mov pc, lr @ back to my caller +ENDPROC(cpu_init_cp15) + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +/************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + *************************************************************************/ +ENTRY(cpu_init_crit) /* * Jump to board specific initialization... * The Mask ROM will have already initialized * basic memory. Go here to bump up clock rate and handle * wake up conditions. */ - mov ip, lr @ persevere link reg across call - bl lowlevel_init @ go setup pll,mux,memory - mov lr, ip @ restore link - mov pc, lr @ back to my caller + b lowlevel_init @ go setup pll,mux,memory +ENDPROC(cpu_init_crit) #endif #ifndef CONFIG_SPL_BUILD