X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fstart.S;h=f5df597e840a0a168ba9223446958c247fa4e74b;hb=83d290c56fab2d38cd1ab4c4cc7099559c1d5046;hp=5ed0f45a26614159328928fbdeac84f692f54d71;hpb=7682a99826a624d3764656b5bb31f88e2f8b235b;p=u-boot diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 5ed0f45a26..f5df597e84 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core * @@ -9,33 +10,45 @@ * Copyright (c) 2003 Richard Woodruff * Copyright (c) 2003 Kshitij * Copyright (c) 2006-2008 Syed Mohammed Khasim - * - * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include #include +#include /************************************************************************* * * Startup Code (reset vector) * - * do important init only if we don't start from memory! - * setup Memory and board specific bits prior to relocation. - * relocate armboot to ram - * setup stack + * Do important init only if we don't start from memory! + * Setup memory and board specific bits prior to relocation. + * Relocate armboot to ram. Setup stack. * *************************************************************************/ .globl reset .globl save_boot_params_ret + .type save_boot_params_ret,%function +#ifdef CONFIG_ARMV7_LPAE + .global switch_to_hypervisor_ret +#endif reset: /* Allow the board to save important registers */ b save_boot_params save_boot_params_ret: +#ifdef CONFIG_ARMV7_LPAE +/* + * check for Hypervisor support + */ + mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 + and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits + cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT) + beq switch_to_hypervisor +switch_to_hypervisor_ret: +#endif /* * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, * except if in HYP mode already @@ -67,7 +80,9 @@ save_boot_params_ret: /* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_cp15 +#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY bl cpu_init_crit +#endif #endif bl _main @@ -102,6 +117,13 @@ ENTRY(save_boot_params) ENDPROC(save_boot_params) .weak save_boot_params +#ifdef CONFIG_ARMV7_LPAE +ENTRY(switch_to_hypervisor) + b switch_to_hypervisor_ret +ENDPROC(switch_to_hypervisor) + .weak switch_to_hypervisor +#endif + /************************************************************************* * * cpu_init_cp15 @@ -165,6 +187,12 @@ ENTRY(cpu_init_cp15) mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_845369 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 22 @ set bit #22 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif + mov r5, lr @ Store my Caller mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR) mov r3, r1, lsr #20 @ get variant field @@ -188,49 +216,88 @@ ENTRY(cpu_init_cp15) skip_errata_798870: #endif +#ifdef CONFIG_ARM_ERRATA_801819 + cmp r2, #0x24 @ Applies to lt including R2p4 + bgt skip_errata_801819 @ skip if not affected rev + cmp r2, #0x20 @ Applies to including and above R2p0 + blt skip_errata_801819 @ skip if not affected rev + mrc p15, 0, r0, c0, c0, 6 @ pick up REVIDR reg + and r0, r0, #1 << 3 @ check REVIDR[3] + cmp r0, #1 << 3 + beq skip_errata_801819 @ skip erratum if REVIDR[3] is set + + mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register + orr r0, r0, #3 << 27 @ Disables streaming. All write-allocate + @ lines allocate in the L1 or L2 cache. + orr r0, r0, #3 << 25 @ Disables streaming. All write-allocate + @ lines allocate in the L1 cache. + push {r1-r5} @ Save the cpu info registers + bl v7_arch_cp15_set_acr + pop {r1-r5} @ Restore the cpu info - fall through +skip_errata_801819: +#endif + #ifdef CONFIG_ARM_ERRATA_454179 + mrc p15, 0, r0, c1, c0, 1 @ Read ACR + cmp r2, #0x21 @ Only on < r2p1 - bge skip_errata_454179 + orrlt r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits - mrc p15, 0, r0, c1, c0, 1 @ Read ACR - orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits push {r1-r5} @ Save the cpu info registers bl v7_arch_cp15_set_acr pop {r1-r5} @ Restore the cpu info - fall through - -skip_errata_454179: #endif #ifdef CONFIG_ARM_ERRATA_430973 + mrc p15, 0, r0, c1, c0, 1 @ Read ACR + cmp r2, #0x21 @ Only on < r2p1 - bge skip_errata_430973 + orrlt r0, r0, #(0x1 << 6) @ Set IBE bit - mrc p15, 0, r0, c1, c0, 1 @ Read ACR - orr r0, r0, #(0x1 << 6) @ Set IBE bit push {r1-r5} @ Save the cpu info registers bl v7_arch_cp15_set_acr pop {r1-r5} @ Restore the cpu info - fall through - -skip_errata_430973: #endif #ifdef CONFIG_ARM_ERRATA_621766 + mrc p15, 0, r0, c1, c0, 1 @ Read ACR + cmp r2, #0x21 @ Only on < r2p1 - bge skip_errata_621766 + orrlt r0, r0, #(0x1 << 5) @ Set L1NEON bit - mrc p15, 0, r0, c1, c0, 1 @ Read ACR - orr r0, r0, #(0x1 << 5) @ Set L1NEON bit push {r1-r5} @ Save the cpu info registers bl v7_arch_cp15_set_acr pop {r1-r5} @ Restore the cpu info - fall through +#endif + +#ifdef CONFIG_ARM_ERRATA_725233 + mrc p15, 1, r0, c9, c0, 2 @ Read L2ACR + + cmp r2, #0x21 @ Only on < r2p1 (Cortex A8) + orrlt r0, r0, #(0x1 << 27) @ L2 PLD data forwarding disable -skip_errata_621766: + push {r1-r5} @ Save the cpu info registers + bl v7_arch_cp15_set_l2aux_ctrl + pop {r1-r5} @ Restore the cpu info - fall through +#endif + +#ifdef CONFIG_ARM_ERRATA_852421 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 24 @ set bit #24 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif + +#ifdef CONFIG_ARM_ERRATA_852423 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 12 @ set bit #12 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif mov pc, r5 @ back to my caller ENDPROC(cpu_init_cp15) -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ + !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) /************************************************************************* * * CPU_init_critical registers