X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fstart.S;h=f5df597e840a0a168ba9223446958c247fa4e74b;hb=83d290c56fab2d38cd1ab4c4cc7099559c1d5046;hp=7b84a7a0f161207611202c7f44544208c70fed13;hpb=11d94319c32cc8590db2f1e186d19f32e652436c;p=u-boot

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 7b84a7a0f1..f5df597e84 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
  *
@@ -9,8 +10,6 @@
  * Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
  * Copyright (c) 2003	Kshitij <kshitij@ti.com>
  * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <asm-offsets.h>
@@ -31,6 +30,7 @@
 
 	.globl	reset
 	.globl	save_boot_params_ret
+	.type   save_boot_params_ret,%function
 #ifdef CONFIG_ARMV7_LPAE
 	.global	switch_to_hypervisor_ret
 #endif
@@ -238,55 +238,47 @@ skip_errata_801819:
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_454179
+	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
+
 	cmp	r2, #0x21		@ Only on < r2p1
-	bge	skip_errata_454179
+	orrlt	r0, r0, #(0x3 << 6)	@ Set DBSM(BIT7) and IBE(BIT6) bits
 
-	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
-	orr	r0, r0, #(0x3 << 6)	@ Set DBSM(BIT7) and IBE(BIT6) bits
 	push	{r1-r5}			@ Save the cpu info registers
 	bl	v7_arch_cp15_set_acr
 	pop	{r1-r5}			@ Restore the cpu info - fall through
-
-skip_errata_454179:
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_430973
+	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
+
 	cmp	r2, #0x21		@ Only on < r2p1
-	bge	skip_errata_430973
+	orrlt	r0, r0, #(0x1 << 6)	@ Set IBE bit
 
-	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
-	orr	r0, r0, #(0x1 << 6)	@ Set IBE bit
 	push	{r1-r5}			@ Save the cpu info registers
 	bl	v7_arch_cp15_set_acr
 	pop	{r1-r5}			@ Restore the cpu info - fall through
-
-skip_errata_430973:
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_621766
+	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
+
 	cmp	r2, #0x21		@ Only on < r2p1
-	bge	skip_errata_621766
+	orrlt	r0, r0, #(0x1 << 5)	@ Set L1NEON bit
 
-	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
-	orr	r0, r0, #(0x1 << 5)	@ Set L1NEON bit
 	push	{r1-r5}			@ Save the cpu info registers
 	bl	v7_arch_cp15_set_acr
 	pop	{r1-r5}			@ Restore the cpu info - fall through
-
-skip_errata_621766:
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_725233
+	mrc	p15, 1, r0, c9, c0, 2	@ Read L2ACR
+
 	cmp	r2, #0x21		@ Only on < r2p1 (Cortex A8)
-	bge	skip_errata_725233
+	orrlt	r0, r0, #(0x1 << 27)	@ L2 PLD data forwarding disable
 
-	mrc	p15, 1, r0, c9, c0, 2	@ Read L2ACR
-	orr	r0, r0, #(0x1 << 27)	@ L2 PLD data forwarding disable
 	push	{r1-r5}			@ Save the cpu info registers
 	bl	v7_arch_cp15_set_l2aux_ctrl
 	pop	{r1-r5}			@ Restore the cpu info - fall through
-
-skip_errata_725233:
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_852421