X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv8%2FKconfig;h=0188b95e99fa64672e88b3ad6289ab26825339fc;hb=4961eafc25d0bfa7ac5f88ec78a7f7501c202fbb;hp=edae43de07dbd2f82b10d2d28a9c38c4d532e85c;hpb=df88cb3b91019e7d7293c73b01a5913a02be9c32;p=u-boot

diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index edae43de07..0188b95e99 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -3,6 +3,24 @@ if ARM64
 config ARMV8_MULTIENTRY
         bool "Enable multiple CPUs to enter into U-Boot"
 
+config ARMV8_SET_SMPEN
+        bool "Enable data coherency with other cores in cluster"
+        help
+	  Say Y here if there is not any trust firmware to set
+	  CPUECTLR_EL1.SMPEN bit before U-Boot.
+
+	  For A53, it enables data coherency with other cores in the
+	  cluster, and for A57/A72, it enables receiving of instruction
+	  cache and TLB maintenance operations.
+	  Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even
+	  for single core systems. Unfortunately write access to this
+	  register may be controlled by EL3/EL2 firmware. To be more
+	  precise, by default (if there is EL2/EL3 firmware running)
+	  this register is RO for NS EL1.
+	  This switch can be used to avoid writing to CPUECTLR_EL1,
+	  it can be safely enabled when EL2/EL3 initialized SMPEN bit
+	  or when CPU implementation doesn't include that register.
+
 config ARMV8_SPIN_TABLE
 	bool "Support spin-table enable method"
 	depends on ARMV8_MULTIENTRY && OF_LIBFDT
@@ -12,8 +30,10 @@ config ARMV8_SPIN_TABLE
 	  To use this feature, you must do:
 	    - Specify enable-method = "spin-table" in each CPU node in the
 	      Device Tree you are using to boot the kernel
-	    - Let secondary CPUs in U-Boot (in a board specific manner)
-	      before the master CPU jumps to the kernel
+	    - Bring secondary CPUs into U-Boot proper in a board specific
+	      manner.  This must be done *after* relocation.  Otherwise, the
+	      secondary CPUs will spin in unprotected memory area because the
+	      master CPU protects the relocated spin code.
 
 	  U-Boot automatically does:
 	    - Set "cpu-release-addr" property of each CPU node
@@ -21,6 +41,47 @@ config ARMV8_SPIN_TABLE
 	    - Reserve the code for the spin-table and the release address
 	      via a /memreserve/ region in the Device Tree.
 
+menu "ARMv8 secure monitor firmware"
+config ARMV8_SEC_FIRMWARE_SUPPORT
+	bool "Enable ARMv8 secure monitor firmware framework support"
+	select OF_LIBFDT
+	select FIT
+	help
+	  This framework is aimed at making secure monitor firmware load
+	  process brief.
+	  Note: Only FIT format image is supported.
+	  You should prepare and provide the below information:
+	    - Address of secure firmware.
+	    - Address to hold the return address from secure firmware.
+	    - Secure firmware FIT image related information.
+	      Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMEWARE_FIT_CNF_NAME
+	    - The target exception level that secure monitor firmware will
+	      return to.
+
+config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
+	bool "Enable ARMv8 secure monitor firmware framework support for SPL"
+	select SPL_OF_LIBFDT
+	select SPL_FIT
+	help
+	  Say Y here to support this framework in SPL phase.
+
+config SEC_FIRMWARE_ARMV8_PSCI
+	bool "PSCI implementation in secure monitor firmware"
+	depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
+	help
+	  This config enables the ARMv8 PSCI implementation in secure monitor
+	  firmware. This is a private PSCI implementation and different from
+	  those implemented under the common ARMv8 PSCI framework.
+
+config ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
+	bool "ARMv8 secure monitor firmware ERET address byteorder swap"
+	depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
+	help
+	  Say Y here when the endianness of the register or memory holding the
+	  Secure firmware exception return address is different with core's.
+
+endmenu
+
 config PSCI_RESET
 	bool "Use PSCI for reset and shutdown"
 	default y
@@ -58,6 +119,16 @@ config ARMV8_PSCI_NR_CPUS
 	  It is no problem to set a larger value than the number of CPUs in
 	  the actual hardware implementation.
 
+config ARMV8_PSCI_CPUS_PER_CLUSTER
+	int "Number of CPUs per cluster"
+	depends on ARMV8_PSCI
+	default 0
+	help
+	  The number of CPUs per cluster, suppose each cluster has same number
+	  of CPU cores, platforms with asymmetric clusters don't apply here.
+	  A value 0 or no definition of it works for single cluster system.
+	  System with multi-cluster should difine their own exact value.
+
 if SYS_HAS_ARMV8_SECURE_BASE
 
 config ARMV8_SECURE_BASE