X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv8%2Fcache.S;h=f1deaa723024e629c8a89aaee9c21bad0dff4a60;hb=79a34b71c943a80af5c6d9a2af736fbb37dcc14c;hp=46f25e63f01d5bf1b4d0cfa137bea638a15484cf;hpb=ba9eb6c7eb3490f72f07bc712f7196fb4e0fe80c;p=u-boot

diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index 46f25e63f0..f1deaa7230 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -150,11 +150,23 @@ ENTRY(__asm_invalidate_icache_all)
 	ret
 ENDPROC(__asm_invalidate_icache_all)
 
-ENTRY(__asm_flush_l3_cache)
+ENTRY(__asm_invalidate_l3_dcache)
 	mov	x0, #0			/* return status as success */
 	ret
-ENDPROC(__asm_flush_l3_cache)
-	.weak	__asm_flush_l3_cache
+ENDPROC(__asm_invalidate_l3_dcache)
+	.weak	__asm_invalidate_l3_dcache
+
+ENTRY(__asm_flush_l3_dcache)
+	mov	x0, #0			/* return status as success */
+	ret
+ENDPROC(__asm_flush_l3_dcache)
+	.weak	__asm_flush_l3_dcache
+
+ENTRY(__asm_invalidate_l3_icache)
+	mov	x0, #0			/* return status as success */
+	ret
+ENDPROC(__asm_invalidate_l3_icache)
+	.weak	__asm_invalidate_l3_icache
 
 /*
  * void __asm_switch_ttbr(ulong new_ttbr)