X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv8%2Fcache.S;h=f1deaa723024e629c8a89aaee9c21bad0dff4a60;hb=79a34b71c943a80af5c6d9a2af736fbb37dcc14c;hp=a9f4fec387feccf2262ef3eef58efe8d838c1d78;hpb=5e2ec773bb6c5acf22d8652112856e87cff86ea4;p=u-boot

diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index a9f4fec387..f1deaa7230 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -14,15 +14,15 @@
 #include <linux/linkage.h>
 
 /*
- * void __asm_flush_dcache_level(level)
+ * void __asm_dcache_level(level)
  *
- * clean and invalidate one level cache.
+ * flush or invalidate one level cache.
  *
  * x0: cache level
- * x1: 0 flush & invalidate, 1 invalidate only
+ * x1: 0 clean & invalidate, 1 invalidate only
  * x2~x9: clobbered
  */
-ENTRY(__asm_flush_dcache_level)
+ENTRY(__asm_dcache_level)
 	lsl	x12, x0, #1
 	msr	csselr_el1, x12		/* select cache level */
 	isb				/* sync change of cssidr_el1 */
@@ -57,14 +57,14 @@ loop_way:
 	b.ge	loop_set
 
 	ret
-ENDPROC(__asm_flush_dcache_level)
+ENDPROC(__asm_dcache_level)
 
 /*
  * void __asm_flush_dcache_all(int invalidate_only)
  *
- * x0: 0 flush & invalidate, 1 invalidate only
+ * x0: 0 clean & invalidate, 1 invalidate only
  *
- * clean and invalidate all data cache by SET/WAY.
+ * flush or invalidate all data cache by SET/WAY.
  */
 ENTRY(__asm_dcache_all)
 	mov	x1, x0
@@ -87,7 +87,7 @@ loop_level:
 	and	x12, x12, #7		/* x12 <- cache type */
 	cmp	x12, #2
 	b.lt	skip			/* skip if no cache or icache */
-	bl	__asm_flush_dcache_level	/* x1 = 0 flush, 1 invalidate */
+	bl	__asm_dcache_level	/* x1 = 0 flush, 1 invalidate */
 skip:
 	add	x0, x0, #1		/* increment cache level */
 	cmp	x11, x0
@@ -104,19 +104,13 @@ finished:
 ENDPROC(__asm_dcache_all)
 
 ENTRY(__asm_flush_dcache_all)
-	mov	x16, lr
 	mov	x0, #0
-	bl	__asm_dcache_all
-	mov	lr, x16
-	ret
+	b	__asm_dcache_all
 ENDPROC(__asm_flush_dcache_all)
 
 ENTRY(__asm_invalidate_dcache_all)
-	mov	x16, lr
 	mov	x0, #0x1
-	bl	__asm_dcache_all
-	mov	lr, x16
-	ret
+	b	__asm_dcache_all
 ENDPROC(__asm_invalidate_dcache_all)
 
 /*
@@ -156,11 +150,23 @@ ENTRY(__asm_invalidate_icache_all)
 	ret
 ENDPROC(__asm_invalidate_icache_all)
 
-ENTRY(__asm_flush_l3_cache)
+ENTRY(__asm_invalidate_l3_dcache)
+	mov	x0, #0			/* return status as success */
+	ret
+ENDPROC(__asm_invalidate_l3_dcache)
+	.weak	__asm_invalidate_l3_dcache
+
+ENTRY(__asm_flush_l3_dcache)
+	mov	x0, #0			/* return status as success */
+	ret
+ENDPROC(__asm_flush_l3_dcache)
+	.weak	__asm_flush_l3_dcache
+
+ENTRY(__asm_invalidate_l3_icache)
 	mov	x0, #0			/* return status as success */
 	ret
-ENDPROC(__asm_flush_l3_cache)
-	.weak	__asm_flush_l3_cache
+ENDPROC(__asm_invalidate_l3_icache)
+	.weak	__asm_invalidate_l3_icache
 
 /*
  * void __asm_switch_ttbr(ulong new_ttbr)