X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv8%2Ffsl-layerscape%2FKconfig;h=2562f4a365188d5eab115902d1ac31605b680674;hb=fb806ad61f8ff10f3abb14dfadfe0f8989665445;hp=b5609ff7a67f018de78f622c99ab4f7d1fd7d9d9;hpb=8dda2e2f9e0976249f4a390e72f12533dbcb5ef4;p=u-boot

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index b5609ff7a6..2562f4a365 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -36,6 +36,7 @@ config ARCH_LS1046A
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_ERRATUM_A008336
 	select SYS_FSL_ERRATUM_A008511
+	select SYS_FSL_ERRATUM_A008850
 	select SYS_FSL_ERRATUM_A009801
 	select SYS_FSL_ERRATUM_A009803
 	select SYS_FSL_ERRATUM_A009942
@@ -73,6 +74,7 @@ config ARCH_LS2080A
 	select SYS_FSL_ERRATUM_A009803
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_A010165
+	select SYS_FSL_ERRATUM_A009203
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 
@@ -89,6 +91,14 @@ config FSL_LSCH3
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 
+config FSL_MC_ENET
+	bool "Management Complex network"
+	depends on ARCH_LS2080A
+	default y
+	select RESV_RAM
+	help
+	  Enable Management Complex (MC) network
+
 menu "Layerscape architecture"
 	depends on FSL_LSCH2 || FSL_LSCH3
 
@@ -126,6 +136,8 @@ config FSL_LS_PPA
 choice
 	prompt "FSL Layerscape PPA firmware loading-media select"
 	depends on FSL_LS_PPA
+	default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
+	default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
 	default SYS_LS_PPA_FW_IN_XIP
 
 config SYS_LS_PPA_FW_IN_XIP
@@ -134,18 +146,46 @@ config SYS_LS_PPA_FW_IN_XIP
 	  Say Y here if the PPA firmware locate at XIP flash, such
 	  as NOR or QSPI flash.
 
+config SYS_LS_PPA_FW_IN_MMC
+	bool "eMMC or SD Card"
+	help
+	  Say Y here if the PPA firmware locate at eMMC/SD card.
+
+config SYS_LS_PPA_FW_IN_NAND
+	bool "NAND"
+	help
+	  Say Y here if the PPA firmware locate at NAND flash.
+
 endchoice
 
 config SYS_LS_PPA_FW_ADDR
 	hex "Address of PPA firmware loading from"
 	depends on FSL_LS_PPA
 	default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
+	default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
 	default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
+	default 0x500000 if SYS_LS_PPA_FW_IN_MMC
+	default 0x500000 if SYS_LS_PPA_FW_IN_NAND
+
 	help
 	  If the PPA firmware locate at XIP flash, such as NOR or
 	  QSPI flash, this address is a directly memory-mapped.
 	  If it is in a serial accessed flash, such as NAND and SD
 	  card, it is a byte offset.
+
+config SYS_LS_PPA_ESBC_ADDR
+	hex "hdr address of PPA firmware loading from"
+	depends on FSL_LS_PPA && CHAIN_OF_TRUST
+	default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
+	default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
+	default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
+	default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
+	help
+	  If the PPA header firmware locate at XIP flash, such as NOR or
+	  QSPI flash, this address is a directly memory-mapped.
+	  If it is in a serial accessed flash, such as NAND and SD
+	  card, it is a byte offset.
+
 endmenu
 
 config SYS_FSL_ERRATUM_A010315
@@ -277,6 +317,16 @@ config SYS_FSL_SDHC_CLK_DIV
 	  clock, in another word SDHC_clk = Platform_clk / this_divider.
 endmenu
 
+config RESV_RAM
+	bool
+	help
+	  Reserve memory from the top, tracked by gd->arch.resv_ram. This
+	  reserved RAM can be used by special driver that resides in memory
+	  after U-Boot exits. It's up to implementation to allocate and allow
+	  access to this reserved memory. For example, the reserved RAM can
+	  be at the high end of physical memory. The reserve RAM may be
+	  excluded from memory bank(s) passed to OS, or marked as reserved.
+
 config SYS_FSL_ERRATUM_A008336
 	bool
 
@@ -289,6 +339,9 @@ config SYS_FSL_ERRATUM_A008585
 config SYS_FSL_ERRATUM_A008850
 	bool
 
+config SYS_FSL_ERRATUM_A009203
+	bool
+
 config SYS_FSL_ERRATUM_A009635
 	bool
 
@@ -297,3 +350,11 @@ config SYS_FSL_ERRATUM_A009660
 
 config SYS_FSL_ERRATUM_A009929
 	bool
+
+config SYS_MC_RSV_MEM_ALIGN
+	hex "Management Complex reserved memory alignment"
+	depends on RESV_RAM
+	default 0x20000000
+	help
+	  Reserved memory needs to be aligned for MC to use. Default value
+	  is 512MB.