X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv8%2Ffsl-layerscape%2FKconfig;h=92e8fa65e438366a9ca3248da881979125f18156;hb=904110c7ac801b99029b2bca4765c792c9eac582;hp=6772584a60422c8c14ee47033e43264d59659e05;hpb=dd2ad2f1318975da1cf64cf95a4a3b3ed44172a5;p=u-boot diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 6772584a60..92e8fa65e4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -1,5 +1,6 @@ config ARCH_LS1012A bool + select ARMV8_SET_SMPEN select FSL_LSCH2 select SYS_FSL_DDR_BE select SYS_FSL_MMDC @@ -7,32 +8,66 @@ config ARCH_LS1012A config ARCH_LS1043A bool + select ARMV8_SET_SMPEN select FSL_LSCH2 + select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 + select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A009660 + select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009929 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_HAS_DDR3 + select SYS_FSL_HAS_DDR4 config ARCH_LS1046A bool + select ARMV8_SET_SMPEN select FSL_LSCH2 + select SYS_FSL_DDR select SYS_FSL_DDR_BE - select SYS_FSL_DDR4 select SYS_FSL_DDR_VER_50 + select SYS_FSL_ERRATUM_A008511 + select SYS_FSL_ERRATUM_A009801 + select SYS_FSL_ERRATUM_A009803 + select SYS_FSL_ERRATUM_A009942 + select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 config ARCH_LS2080A bool + select ARMV8_SET_SMPEN select FSL_LSCH3 - select SYS_FSL_DDR4 + select SYS_FSL_DDR select SYS_FSL_DDR_LE select SYS_FSL_DDR_VER_50 select SYS_FSL_HAS_DP_DDR + select SYS_FSL_HAS_SEC + select SYS_FSL_HAS_DDR4 + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE select SYS_FSL_SRDS_2 + select SYS_FSL_ERRATUM_A008336 + select SYS_FSL_ERRATUM_A008511 + select SYS_FSL_ERRATUM_A008514 + select SYS_FSL_ERRATUM_A008585 + select SYS_FSL_ERRATUM_A009635 + select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009801 + select SYS_FSL_ERRATUM_A009803 + select SYS_FSL_ERRATUM_A009942 + select SYS_FSL_ERRATUM_A010165 config FSL_LSCH2 bool + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_BE select SYS_FSL_SRDS_1 select SYS_HAS_SERDES @@ -44,8 +79,37 @@ config FSL_LSCH3 menu "Layerscape architecture" depends on FSL_LSCH2 || FSL_LSCH3 -config SYS_FSL_MMDC - bool +config FSL_PCIE_COMPAT + string "PCIe compatible of Kernel DT" + depends on PCIE_LAYERSCAPE + default "fsl,ls1012a-pcie" if ARCH_LS1012A + default "fsl,ls1043a-pcie" if ARCH_LS1043A + default "fsl,ls1046a-pcie" if ARCH_LS1046A + default "fsl,ls2080a-pcie" if ARCH_LS2080A + help + This compatible is used to find pci controller node in Kernel DT + to complete fixup. + +menu "Layerscape PPA" +config FSL_LS_PPA + bool "FSL Layerscape PPA firmware support" + depends on !ARMV8_PSCI + depends on ARCH_LS1043A || ARCH_LS1046A + select FSL_PPA_ARMV8_PSCI + help + The FSL Primary Protected Application (PPA) is a software component + which is loaded during boot stage, and then remains resident in RAM + and runs in the TrustZone after boot. + Say y to enable it. + +config FSL_PPA_ARMV8_PSCI + bool "PSCI implementation in PPA firmware" + depends on FSL_LS_PPA + help + This config enables the ARMv8 PSCI implementation in PPA firmware. + This is a private PSCI implementation and different from those + implemented under the common ARMv8 PSCI framework. +endmenu config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" @@ -66,11 +130,6 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. -config NUM_DDR_CONTROLLERS - int "Maximum DDR controllers" - default 3 if ARCH_LS2080A - default 1 - config SECURE_BOOT bool help @@ -102,49 +161,102 @@ config SYS_FSL_SRDS_2 config SYS_HAS_SERDES bool -config SYS_FSL_DDR - bool "Freescale DDR driver" +endmenu + +menu "Layerscape clock tree configuration" + depends on FSL_LSCH2 || FSL_LSCH3 + +config SYS_FSL_CLK + bool "Enable clock tree initialization" + default y + +config CLUSTER_CLK_FREQ + int "Reference clock of core cluster" + depends on ARCH_LS1012A + default 100000000 help - Select Freescale General DDR driver, shared between most Freescale - PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- - based Layerscape SoCs (such as ls2080a). + This number is the reference clock frequency of core PLL. + For most platforms, the core PLL and Platform PLL have the same + reference clock, but for some platforms, LS1012A for instance, + they are provided sepatately. -config SYS_FSL_DDR_BE - bool +config SYS_FSL_PCLK_DIV + int "Platform clock divider" + default 1 if ARCH_LS1043A + default 1 if ARCH_LS1046A + default 2 help - Access DDR registers in big-endian. + This is the divider that is used to derive Platform clock from + Platform PLL, in another word: + Platform_clk = Platform_PLL_freq / this_divider -config SYS_FSL_DDR_LE - bool +config SYS_FSL_DSPI_CLK_DIV + int "DSPI clock divider" + default 1 if ARCH_LS1043A + default 2 help - Access DDR registers in little-endian. + This is the divider that is used to derive DSPI clock from Platform + PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider. -config SYS_FSL_DDR_VER - int - default 50 if SYS_FSL_DDR_VER_50 +config SYS_FSL_DUART_CLK_DIV + int "DUART clock divider" + default 1 if ARCH_LS1043A + default 2 + help + This is the divider that is used to derive DUART clock from Platform + clock, in another word DUART_clk = Platform_clk / this_divider. -config SYS_FSL_DDR_VER_50 +config SYS_FSL_I2C_CLK_DIV + int "I2C clock divider" + default 1 if ARCH_LS1043A + default 2 + help + This is the divider that is used to derive I2C clock from Platform + clock, in another word I2C_clk = Platform_clk / this_divider. + +config SYS_FSL_IFC_CLK_DIV + int "IFC clock divider" + default 1 if ARCH_LS1043A + default 2 + help + This is the divider that is used to derive IFC clock from Platform + clock, in another word IFC_clk = Platform_clk / this_divider. + +config SYS_FSL_LPUART_CLK_DIV + int "LPUART clock divider" + default 1 if ARCH_LS1043A + default 2 + help + This is the divider that is used to derive LPUART clock from Platform + clock, in another word LPUART_clk = Platform_clk / this_divider. + +config SYS_FSL_SDHC_CLK_DIV + int "SDHC clock divider" + default 1 if ARCH_LS1043A + default 1 if ARCH_LS1012A + default 2 + help + This is the divider that is used to derive SDHC clock from Platform + clock, in another word SDHC_clk = Platform_clk / this_divider. +endmenu + +config SYS_FSL_ERRATUM_A008336 bool -config SYS_FSL_DDRC_ARM_GEN3 +config SYS_FSL_ERRATUM_A008514 bool -config SYS_FSL_DDRC_GEN4 +config SYS_FSL_ERRATUM_A008585 bool -config SYS_FSL_DDR3 - bool "Freescale DDR3 controller" - depends on !SYS_FSL_DDR4 - select SYS_FSL_DDR - select SYS_FSL_DDRC_ARM_GEN3 - help - Enable Freescale DDR3 controller on ARM-based SoCs. +config SYS_FSL_ERRATUM_A008850 + bool -config SYS_FSL_DDR4 - bool "Freescale DDR4 controller" - select SYS_FSL_DDR - select SYS_FSL_DDRC_GEN4 - help - Enable Freescale DDR4 controller. +config SYS_FSL_ERRATUM_A009635 + bool -endmenu +config SYS_FSL_ERRATUM_A009660 + bool + +config SYS_FSL_ERRATUM_A009929 + bool