X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv8%2Ffsl-layerscape%2Ffsl_lsch3_serdes.c;h=955e0b747854383a1de097f886d7aafae30fbf48;hb=a9a5cef391ed5b2e47ed02a8cecf0ab1a19fc76a;hp=9110d7a7438023bda17b015241f6e395c5c4537b;hpb=71fe22256cc9eb5decdd98842ec030ba921cd321;p=u-boot

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index 9110d7a743..955e0b7478 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/soc.h>
 #include <fsl-mc/ldpaa_wriop.h>
@@ -23,6 +23,11 @@ int xfi_dpmac[XFI8 + 1];
 int sgmii_dpmac[SGMII16 + 1];
 #endif
 
+__weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
+{
+	return;
+}
+
 int is_serdes_configured(enum srds_prtcl device)
 {
 	int ret = 0;
@@ -46,20 +51,22 @@ int is_serdes_configured(enum srds_prtcl device)
 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-	u32 cfg = gur_in32(&gur->rcwsr[28]);
+	u32 cfg = 0;
 	int i;
 
 	switch (sd) {
 #ifdef CONFIG_SYS_FSL_SRDS_1
 	case FSL_SRDS_1:
-		cfg &= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
-		cfg >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+		cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
+		cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
+		cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
 		break;
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
 	case FSL_SRDS_2:
-		cfg &= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
-		cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+		cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
+		cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
+		cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
 		break;
 #endif
 	default:
@@ -78,8 +85,8 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 	return -ENODEV;
 }
 
-void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
-		u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
+void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
+		 u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	u32 cfg;
@@ -90,7 +97,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 
 	memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
 
-	cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask;
+	cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
 	cfg >>= sd_prctl_shift;
 	printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
 
@@ -106,28 +113,10 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 #ifdef CONFIG_FSL_MC_ENET
 			switch (lane_prtcl) {
 			case QSGMII_A:
-				wriop_init_dpmac(sd, 5, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 6, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 7, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 8, (int)lane_prtcl);
-				break;
 			case QSGMII_B:
-				wriop_init_dpmac(sd, 1, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 2, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 3, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 4, (int)lane_prtcl);
-				break;
 			case QSGMII_C:
-				wriop_init_dpmac(sd, 13, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 14, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 15, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 16, (int)lane_prtcl);
-				break;
 			case QSGMII_D:
-				wriop_init_dpmac(sd, 9, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 10, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 11, (int)lane_prtcl);
-				wriop_init_dpmac(sd, 12, (int)lane_prtcl);
+				wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
 				break;
 			default:
 				if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
@@ -165,15 +154,17 @@ void fsl_serdes_init(void)
 #ifdef CONFIG_SYS_FSL_SRDS_1
 	serdes_init(FSL_SRDS_1,
 		    CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
-		    FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK,
-		    FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT,
+		    FSL_CHASSIS3_SRDS1_REGSR,
+		    FSL_CHASSIS3_SRDS1_PRTCL_MASK,
+		    FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
 		    serdes1_prtcl_map);
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
 	serdes_init(FSL_SRDS_2,
 		    CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
-		    FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK,
-		    FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT,
+		    FSL_CHASSIS3_SRDS2_REGSR,
+		    FSL_CHASSIS3_SRDS2_PRTCL_MASK,
+		    FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
 		    serdes2_prtcl_map);
 #endif
 }