X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv8%2Ffsl-layerscape%2Flowlevel.S;h=3136e3f3a2ac52d631b3d6942fbcfc904e823d91;hb=5619295995e3262bb5770e8b5e945ffdc5442145;hp=f4273561040f9deede84f2c0bb5d99a907b09b3b;hpb=4f66e09bb9fbc47b73f67c3cc08ee2663e8fcdb1;p=u-boot

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index f427356104..3136e3f3a2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -73,6 +73,9 @@ ENDPROC(smp_kick_all_cpus)
 ENTRY(lowlevel_init)
 	mov	x29, lr			/* Save LR */
 
+	switch_el x1, 1f, 100f, 100f	/* skip if not in EL3 */
+1:
+
 #ifdef CONFIG_FSL_LSCH3
 
 	/* Set Wuo bit for RN-I 20 */
@@ -193,6 +196,7 @@ ENTRY(lowlevel_init)
 #endif
 #endif
 
+100:
 	branch_if_master x0, x1, 2f
 
 #if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
@@ -201,6 +205,8 @@ ENTRY(lowlevel_init)
 #endif
 
 2:
+	switch_el x1, 1f, 100f, 100f	/* skip if not in EL3 */
+1:
 #ifdef CONFIG_FSL_TZPC_BP147
 	/* Set Non Secure access for all devices protected via TZPC */
 	ldr	x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
@@ -266,8 +272,11 @@ ENTRY(lowlevel_init)
 	isb
 	dsb	sy
 #endif
+100:
 1:
 #ifdef CONFIG_ARCH_LS1046A
+	switch_el x1, 1f, 100f, 100f	/* skip if not in EL3 */
+1:
 	/* Initialize the L2 RAM latency */
 	mrs   x1, S3_1_c11_c0_2
 	mov   x0, #0x1C7
@@ -279,6 +288,7 @@ ENTRY(lowlevel_init)
 	orr   x1,  x1, #0x80
 	msr   S3_1_c11_c0_2, x1
 	isb
+100:
 #endif
 
 #if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
@@ -379,11 +389,14 @@ ENTRY(__asm_flush_l3_dcache)
 	/*
 	 * Return status in x0
 	 *    success 0
-	 *    tmeout 1 for setting SFONLY, 2 for FAM, 3 for both
+	 *    timeout 1 for setting SFONLY, 2 for FAM, 3 for both
 	 */
 	mov	x29, lr
 	mov	x8, #0
 
+	switch_el x0, 1f, 100f, 100f	/* skip if not in EL3 */
+
+1:
 	dsb	sy
 	mov	x0, #0x1		/* HNFPSTAT_SFONLY */
 	bl	hnf_set_pstate
@@ -401,6 +414,7 @@ ENTRY(__asm_flush_l3_dcache)
 	bl	hnf_pstate_poll
 	cbz	x0, 1f
 	add	x8, x8, #0x2
+100:
 1:
 	mov	x0, x8
 	mov	lr, x29
@@ -483,9 +497,7 @@ slave_cpu:
 	rev     x0, x0                  /* BE to LE conversion */
 cpu_is_le:
 	ldr	x5, [x11, #24]
-	ldr	x6, =IH_ARCH_DEFAULT
-	cmp	x6, x5
-	b.eq	1f
+	cbz	x5, 1f
 
 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
 	adr	x4, secondary_switch_to_el1
@@ -527,9 +539,7 @@ ENTRY(secondary_switch_to_el1)
 	ldr	x4, [x11]
 
 	ldr	x5, [x11, #24]
-	ldr	x6, =IH_ARCH_DEFAULT
-	cmp	x6, x5
-	b.eq	2f
+	cbz	x5, 2f
 
 	ldr	x5, =ES_TO_AARCH32
 	bl	switch_to_el1