X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv8%2Ffsl-layerscape%2Fsoc.c;h=9e3cdd78af5b6f70fffc9298801c69331f599462;hb=fb806ad61f8ff10f3abb14dfadfe0f8989665445;hp=b54a9379711752e1dd78184121884954b08d4ff5;hpb=02ccab1908c405fe1449457d4a0d343784a30acb;p=u-boot

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index b54a937971..9e3cdd78af 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -152,6 +152,7 @@ static void erratum_rcw_src(void)
  * This erratum requires setting glitch_en bit to enable
  * digital glitch filter to improve clock stability.
  */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
 static void erratum_a009203(void)
 {
 	u8 __iomem *ptr;
@@ -178,6 +179,7 @@ static void erratum_a009203(void)
 #endif
 #endif
 }
+#endif
 
 void bypass_smmu(void)
 {
@@ -191,7 +193,9 @@ void fsl_lsch3_early_init_f(void)
 {
 	erratum_rcw_src();
 	init_early_memctl_regs();	/* tighten IFC timing */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
 	erratum_a009203();
+#endif
 	erratum_a008514();
 	erratum_a008336();
 #ifdef CONFIG_CHAIN_OF_TRUST