X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv8%2Fstart.S;h=62d97f7e882225a027390e8d2b6f13c4a6a606de;hb=4961eafc25d0bfa7ac5f88ec78a7f7501c202fbb;hp=953505735523d07a9c251b0d269502056b881645;hpb=cc422dae217924d9fe63258e39d309d84d70d437;p=u-boot

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 9535057355..62d97f7e88 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -85,6 +85,17 @@ save_boot_params_ret:
 	msr	cpacr_el1, x0			/* Enable FP/SIMD */
 0:
 
+	/*
+	 * Enalbe SMPEN bit for coherency.
+	 * This register is not architectural but at the moment
+	 * this bit should be set for A53/A57/A72.
+	 */
+#ifdef CONFIG_ARMV8_SET_SMPEN
+	mrs     x0, S3_1_c15_c2_1               /* cpuactlr_el1 */
+	orr     x0, x0, #0x40
+	msr     S3_1_c15_c2_1, x0
+#endif
+
 	/* Apply ARM core specific erratas */
 	bl	apply_core_errata
 
@@ -250,14 +261,14 @@ WEAK(lowlevel_init)
 	/*
 	 * All slaves will enter EL2 and optionally EL1.
 	 */
-	adr	x3, lowlevel_in_el2
-	ldr	x4, =ES_TO_AARCH64
+	adr	x4, lowlevel_in_el2
+	ldr	x5, =ES_TO_AARCH64
 	bl	armv8_switch_to_el2
 
 lowlevel_in_el2:
 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
-	adr	x3, lowlevel_in_el1
-	ldr	x4, =ES_TO_AARCH64
+	adr	x4, lowlevel_in_el1
+	ldr	x5, =ES_TO_AARCH64
 	bl	armv8_switch_to_el1
 
 lowlevel_in_el1: